Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

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I have not modified the VHDL output file (.vho) by removing the reference to the Standard Delay Format Output File (.sdo). So why am I getting this er...

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Do you think that Intel stole the idea of the Thunderbolt port from my Uncle's patent?

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VCXO replacement AN 746

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1681

Arria 10 HPS peripheral routing - EMAC/MDIO - Shared IO/FPGA IO

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Hey, I would like to use HyperBus memory. My board will contain cyclone V too. My question is, how the clock pin in the HyperBus should be connecte...

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We are using Altera Cyclone IV EP4CE10. Does it provide SPI based FPGA programming as Xilinx provides?

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How do I develop with a legacy CPLD Max3000a?

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1150

PCIe: Which devices supports more then one Virtual Channel (VC)?

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2204

i am using MAX 10 with external CFI NOR flash for FPGA ST10 image. for FPGA configuration using "PFL II IP core " . the problem is how we can ...

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Replacement for LXT905

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1925

Intel Arria 10 GX FPGA (DK-ACB-10AX1152AES) compatible with Dell R540 ?

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1199

Interface LVDS signals to the FPGA cyclone V GX.

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do you need different drivers for reference clocks for A10GX?

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Cyclone 10 GX: unused GX Transceiver

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USB Blaster I is working but USB blaster II NOT working? (important)

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Programmable Devices

Discussions

I have not modified the VHDL output file (.vho) by removing the reference to the Standard Delay Format Output File (.sdo). So why am I getting this er...

Do you think that Intel stole the idea of the Thunderbolt port from my Uncle's patent?

VCXO replacement AN 746

Arria 10 HPS peripheral routing - EMAC/MDIO - Shared IO/FPGA IO

Hey, I would like to use HyperBus memory. My board will contain cyclone V too. My question is, how the clock pin in the HyperBus should be connecte...

We are using Altera Cyclone IV EP4CE10. Does it provide SPI based FPGA programming as Xilinx provides?

How do I develop with a legacy CPLD Max3000a?

PCIe: Which devices supports more then one Virtual Channel (VC)?

i am using MAX 10 with external CFI NOR flash for FPGA ST10 image. for FPGA configuration using "PFL II IP core " . the problem is how we can ...

Replacement for LXT905

Intel Arria 10 GX FPGA (DK-ACB-10AX1152AES) compatible with Dell R540 ?

Interface LVDS signals to the FPGA cyclone V GX.

do you need different drivers for reference clocks for A10GX?

Cyclone 10 GX: unused GX Transceiver

USB Blaster I is working but USB blaster II NOT working? (important)

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Re: Download speed