I need to repurpose some IO in a HPS Shared IO sub-bank that contains the MDIO pins. These repurposed pins need to be driven from the FPGA fabric. A Shared IO sub-bank cannot only be HPS-driven OR FPGA-driven.
I could route the MAC (RGMII) through the FPGA but Arria 10 does not support RGMII from the FPGA. It won't close timing (see KDB).
Is it possible to route the MAC pins to Shared IO and the MDIO to the FPGA where they can route through the FPGA to other IO?
Can the I2C_EMAC be used in a MDIO-mode? (and therefore be routed to the FPGA).
I could drop a MDIO core in the FPGA off the lwh2f bridge but the preferred path is to use the working software when everything is Shared IO.
SO --- can the peripheral muxing separate the MAC from the MDIO for pin routing purposes?
You cannot do RGMII via the FPGA.
I looked into routing MDIO to FPGA and RGMII to the Shared IO. Could not find a solution.
I tried routing EMAC0 to shared IO with the MDIO off. I then tried routing EMAC1 (which I do not need) to the FPGA just for the MDIO. This became too involved in software to get EMAC0 to use the MDIO of EMAC1. I would think there would be some example of how to do this as dual or quad PHYs would use 1 MDIO for multiple MAC.
Ultimately I found we had the trace pins reserved with resistors to open pads on the PCB. As we were not using the trace we re-purposed by tacking wire to the resistor pads.