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Valued Contributor III
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[VHDL] Synthesis of 'if' loop(s)

Hello, I have a specific problem. 

Does a number of instructions under if loop affect synthesis and fitter results? For example, I have a several simple instructions, such as adding or several shifters - independent from each other - and I put them all under one process(clk). Could fitter results be different, if I divide it and put all groups of dependent registers under separate processes? 

 

For example, change process: 

 

process(clk) begin if rising_edge(clk) then a0 <= a1; a1 <= a2; b0 <= b1; b1 <= b2; end if; end process;into: 

 

process(clk) begin if rising_edge(clk) then a0 <= a1; a1 <= a2; end if; end process; process(clk) begin if rising_edge(clk) then b0 <= b1; b1 <= b2; end if; end process;Thanks, 

Sz.
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Valued Contributor III

Re: [VHDL] Synthesis of 'if' loop(s)

if .. then constructs haven't to do with iteration loops. 

 

Generally, I would expect that the synthesis results of exactly functional equivalent logic constructs would be independent of grouping it into processes. Independent logic branches would be synthesized separately in any case. 

 

In my opinion, the most important aspect is readability of behavioral code. Related operations should be grouped together.
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Valued Contributor III

Re: [VHDL] Synthesis of 'if' loop(s)

The two bits of code you posted would provide identical results, but personally I would just use the first process and separate the two shifters with some good comments, saying they are different shifters. 

 

The synthesisor/fitter does a very good job at combining related logic, whether its in the same if block or not, or whether its in completly separate processes. The synthesisor basically does and massive boolean equation reduction. If statements boil down to simple logic gates.  

 

Great examples of where synthesis and fitter results can differ - if you have several memories all addressed using the same address bus, the RTL viewer will show several separate altsyncrams, but when fitted it may use only a single M9K. It is very good at packing.
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Valued Contributor III

Re: [VHDL] Synthesis of 'if' loop(s)

Ok, thanks very much, I wasn't sure about this. I just need to know any things, that may affect design.

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