[VHDL] Using the same register on many processes

[Altera_Forum]

Hi. 

If i have a code like:  signal counter: integer etc; PROCESS (clock25) BEGIN if (clock25 = '1') then counter <= counter +1; ... end if; ... END process; PROCESS (clock25, ...) BEGIN if (counter = etc) then .... END PROCESS;   Can be a timing violation if the second process is executed because clock25 is rising up?

[Altera_Forum]

The question isn't clear. The second process is combinational, as far shown. A timing violation can only occur in an edge triggered process.

[Altera_Forum]

--- Quote Start ---  The question isn't clear. The second process is combinational, as far shown. A timing violation can only occur in an edge triggered process.  --- Quote End ---     I've this code:   signal vsync_count : integer range 0 to 799; signal hsync_count : integer range 0 to 520; signal clock25 : std_logic; PROCESS (clock25) BEGIN IF (clock25 = '1') THEN hsync_count <= hsync_count+1; if (hsync_count < 96) then hsync <= '1'; else hsync <= '0'; end if; END IF; END PROCESS; PROCESS (clock25) begin if (clock25 = '1') then if (hsync_count >= 144 ) and (hsync_count < 784 ) and (vsync_count >= 39 ) and (vsync_count < 519 ) then rgboe <= '0'; else rgboe <= '1'; end if; end if; end process; Are you sure that the 2nd process can't do a timing violation with hsync_count register? It's a safe design this? Thank you

[Altera_Forum]

Depends on what you regard as safe. Generally, the combinational output of process 2 can be expected to have glitches, because it's not registered. In this special case, rgboe is permanently '1' because hsync_count never reaches 144 and the first condition is always false. 

 Please also consider, that the sensitivity list of process 2 has no actual effect in synthesis, although Quartus II complains if it's missing.

[Altera_Forum]

--- Quote Start ---  Depends on what you regard as safe. Generally, the combinational output of process 2 can be expected to have glitches, because it's not registered. In this special case, rgboe is permanently '1' because hsync_count never reaches 144 and the first condition is always false.  Please also consider, that the sensitivity list of process 2 has no actual effect in synthesis, although Quartus II complains if it's missing.  --- Quote End ---    Uhm, i want the output registered! With this code:   PROCESS (clock25) begin if (clock25'event and clock25 = '1') then if (hsync_count >= 144 ) and (hsync_count < 784 ) and (vsync_count >= 39 ) and (vsync_count < 519 ) then rgboe <= '0'; else rgboe <= '1'; end if; end if; end process;   the combinational output is registered right? When this process is executed, there is a reading in hsync_count register. But the first process is writing a new value inside this register. So, can be a timing violation or Quartus avoid this situation? Thank you

[Altera_Forum]

The result from changed hsync_count value arrives at the rgboe register input after the clock edge. That's how simple synchronous FPGA logic with a common clock domain works. The Quartus timing analysis still has to check for two possible problems: 

- delay differences in the clock network - the logic delay between hsync_count registers and rgboe registers must be shorter than a clock period minus hold time.