VHDL VERILOG Pin Planner and Quartus II -- case sensitivity trouble --

[Altera_Forum]

I downloaded Linux application for DECA MAX 10 Arrow board, first test loading prebuilt .sof it work, then I extracted all code from compressed archive, I also built and downloaded new time limited sof and it work, problem TOP level is Verilog written and I am not proficient in this languages, so I read it, I understand simple programs, top level is not so distant from. 

Then I try'd copy top to a new file and I added my port definition translating in VHDL, ok translation I don't know why don't boot Linux and still don't start processor core, the strange was that my own modules are perfectly working...    After some pain I try'd a new way, just patching Verilog, top level is so simple I guess I was able to write a patch.  Goal was to use 4Dimension LCD CAPE on this board, so again I got the code for my module from VHDL and pasted on Verilog file, Ok this time Linux boot Up, I am not able to use button from LCD board and LCD was white and without synk.   Looking at Pin planner two kind of pin definition for GPIO_D where present, the board default definition and some lower case.. SO I learnt that casing is important:    VHDL is not case sensitive but casing is exported to Pin Planner    Verilog is CASE Sensitive as in c it resemble.   Pin Planner and scripting languages are case sensitive so TOP level Entity port definition in VHDL need be written with casing exactly as in pin planner or scripting.   VHDL after this discover still doesn't work for unknown reason I discovered again on Pin planner, porting from Verilog some mem_ signal where [0:0] vectors, VHDL require declaration as std_logic_vector(0 downto 0), it compile but again pin got unassigned on pin planner for some signals only.  On top level these signals again need be declared as STD_LOGIC, after this the problem arises from assignment, Verilog accept export vector[0:0] and automatically (Danger!!)    Both files are attached on this thread, LCD signals are from my modules, now both work on VHDL and Verilog too.  version 15.1 of quartus II on Linux has trouble with pin planner both in graphical interface and pin assignment, also speed is decreased a lot from version 15.0, usage of parallel processing is less intensive.   compiling image require about 15 minutes so test are limited by time.

[Altera_Forum]

Step 2, after too much struggle about no idea what can be wrong, included here as attachment are two images of pin planner one from VHDL top and one from Verilog, I cannot see differences nor I am able to grasp what is different from top level module interface seems quite similar and signals are assigned same manner. 

 Original Verilog  assign mdio_in = NET_MDIO;  assign NET_MDIO = mdio_oen == 0 ? mdio_out : 1'bz;   Translated VHDL:   mdio_in <= NET_MDIO;  NET_MDIO <=   mdio_out when mdio_oen = '0'  else 'Z';   One thing left me astonished is that an output signal got assigned to a value from verilog, VHDL report error and I agree.  Verilog assign a value to output:  .tse_mac_status_connection_ena_10 ( 1'b1 ),   VHDL report error  tse_mac_status_connection_ena_10 => '1' , -- : out std_logic