FT232RL as a clock for a Acex EP1K50TC144-3 fpga

[Altera_Forum]

Hi, 

 This is my first post on the Altera forum :)  I don't know if there is someone who has knowledge using an "old" Acex EP1K50TC144-3 fpga.  I'm using a FT232RL chip which is capable of outputting 6,12,24,48MHz clock signals on the CBUS4 output pin. If I connect the input fpga Pin125 (Dedicated Clock Pin) to the output CBUS4 pin from FT232RL chip using a pull-up resistor of 560ohms I'm not getting the needed logic voltages above 6Mhz. I need 48MHz clock for the fpga.   Do I need a larger pull-up or are there extra configurations needed in Quartus II 9.0.  Any ideas?  Thanks

[Altera_Forum]

Why do you need the pull-up? CBUS4 contains a complete buffer and shouldn't need any external pull-up. The 560R you mention could well be loading the signal such that it's shape changes. Have you tried removing it? 

 You're certainly right to take it into a dedicated clock pin. This shouldn't load the CBUS4 buffer unduly. I assume you don't have anything else loading this net? And you're powering the bank that the dedicated clock pin resides in at 3.3V?  Happy New Year, Alex

[Altera_Forum]

Hi Alex, 

 Thanks for the reply! Happy New year!  Fpga VCC_CLK pin 53 is connected to 3V3   I got a clock at 6Mhz, but when I set the FT232RL at 12Mhz output, my clock is there but seams to be unstable? I removed the 560ohm pull-up.  The input fpga Pin125 (Dedicated Clock Pin at FT232 out 48Mhz) is also connected to pin 126 (Dedicated Input) I want to divide my clock by 4 (48/4= 12Mhz) and send it to pin 55 (Dedicated Clock Pin=12Mhz) to divide it for my rs232 I/O baud clock (12/64=187500 baud)  Higher than 6Mhz reduces my input voltage levels to the fpga clock input. Any other ideas? I assumed the fpga input needed a pull-up?   Thanks

[Altera_Forum]

I'm afraid 3.3V on VCC_CKLK doesn't sound right. Your -3 part doesn't support the ClockLock/ClockBoost circuit and PLL for which this pin is relevant. I assume you're not using the PLL (which I don't believe your device has)? In which case this pin should be connected to VCCINT - 2.5V. I doubt that's the cause of your issue. However, it could result in damage to the FPGA. 

 I'm not sure I understand your description of your circuit topology. Does your CBUS4 signal feed both FPGA pins 125 & 126? If so, that shouldn't be much of a problem. However, I'd recommend it only feeds one of the dedicated clock pins - 55 or 125. That's enough to allow you to generate your divided clocks - there's no need to feed the signal to an additional pin.    --- Quote Start ---  my clock is there but seams to be unstable  --- Quote End ---   Can you lift the FTDI pin, such that it's not being loaded, and see what the clock looks like? It should be perfect. Assuming so then something in your circuit is loading it too much.    --- Quote Start ---  I want to divide my clock by 4 (48/4= 12Mhz) and send it to pin 55  --- Quote End ---   Pin 55 is a dedicated input pin. So, you can't feed a generated clock signal out of it. If you want to feed it out of the FPGA you'll need to use another pin.    --- Quote Start ---  I assumed the fpga input needed a pull-up?  --- Quote End ---   No. That's not the (necessarily) case. If your clock source can go tri-state then a pull-up could be considered good practice to ensure the FPGA doesn't misbehave. However, a 10kR resistor, or higher, would be sufficient.  Cheers, Alex

[Altera_Forum]

Hi Alex, 

 I had contact with FTDI support and the solution was to drive the I/O with higher current setting in the FT232RL EEPROM configuration.  Got no PULL-UP and the clock is running 48Mhz and connected to both 125, 126 pins. Signal is divided and set on output pin 51. This pin 51 is external routed to pin 55.  Don't know if it works with a PULL-UP?  Indeed, -3 part doesn't support the ClockLock/ClockBoost circuit and PLL.   Thanks for the reply!