VHDL adding two registers

Altera_Forum · ‎04-03-2009

I am trying to add two registers together so that A=A+B. The code I have compiles, but when I simulate, I do not get the expected result. Can someone help me?


Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity  Four_Bit_Register is
    Port (
        Clear        : in  std_logic;
        Inc           : in  std_logic; -- x
        Clock       : in  std_logic;
        Cnt_in        : in std_logic_vector(3 downto 0);       
        Cnt_out        : out std_logic_vector(3 downto 0);
        Load        : in std_logic);    
End Four_Bit_Register;
Architecture Four_Bit_Register_Arch of Four_Bit_Register is
 
Signal Cnt,A,B : std_logic_vector (3 downto 0);    
Begin
 Cnt_out <= Cnt;
  
  Count : Process( Clear, Inc, Clock, Load)
  
Begin
   
    if clock'event and Clock = '1' then
       A<=A+B;
    if Clear = '1' then
             Cnt    <= "0000";
    elsif Load = '1' then 
        Cnt <= Cnt_in;
    elsif Inc= '1' then
              Cnt    <= Cnt + "0001";
         else
             Cnt    <= Cnt;
            End if;    
End if;
End process;
end Four_Bit_Register_Arch;

Altera_Forum · ‎04-03-2009

Well for one thing A (and B) don't have any initial values set through a reset nor do they appear to get values from anywhere, except maybe 'UU..U' . How do you expect to get a value when you have no source to provide them with a value?

Altera_Forum · ‎04-03-2009

I see what you are saying. What I am trying to do is define to registers (A and B), both with the same architecture and add those together. So I need two registers of the same kind that I defined in the start of my program

Altera_Forum · ‎04-03-2009

Right, and what I'm saying is you'll get undefined for your std_logic_vector because you never give them anything to actually add. A synthesizer will simply optimize these out of existence because they don't do anything. What you are doing should be fine provided that you give them values in some manner, as well as provide an output for A to go to.