[VHDL] 'else generate' is not supported ...

[Altera_Forum]

Hi All, 

 I'm receiving the following error during my code compilation:  (vcom-1440) Language feature ELSE GENERATE STATEMENT is not supported yet  From what Quartus version is this feature supported?   Here is my code:  gen_flr_cnt : if (tbl(i).sbit = flr_cnt or tbl(i).pbit = flr_cnt or tbl(i).ibit = flr_cnt) generate i_flr_cnt : entity work.flr_cnt generic map( TRSH =>FLR_CNT_TRSH ) port map( clk => clk, rstn => rstn, clr => cnt_clr, flr_in => bit_vec(i), flr_out => flr_cnt_res(i) ); else generate flr_cnt_res(i) <= '0'; end generate gen_flr_cnt;   Thank you!

[Altera_Forum]

You are ahead of vhdl standards. You can split generate into two sections: 

if true generate ... end generate;  if false generate ... end generate;

[Altera_Forum]

I was under the impression that else generate had been supported for a while. What quartus version are you using. 

 I am a bit suspicious of your generate expression though. Is it really static?

[Altera_Forum]

--- Quote Start ---  You are ahead of vhdl standards. You can split generate into two sections: if true generate ... end generate;  if false generate ... end generate;  --- Quote End ---    Vhdl 2008 supports if..else generate and case generate. Quartus has supported it since at least q15  http://quartushelp.altera.com/15.0/mergedprojects/hdl/vhdl/vhdl_list_2008_vhdl_support.htm

[Altera_Forum]

What quartus version are you using" - Quartus v16  

 I am a bit suspicious of your generate expression though. Is it really static?" - yes, all elements inside of 'if' are constants

[Altera_Forum]

Well if it's saying it's not supported, you'll have to use separate generate statements.

[Altera_Forum]

Actually I tried this sintax in another Quartus 16 and it passed there...  

 Any clue? In both the file was defined as VHDL-2008  How could it be?

[Altera_Forum]

Standard edition or Pro? I think it may be a Pro edition only feature.

[Altera_Forum]

Quartus SJ Standard Edition... What is "SJ"?

[Altera_Forum]

Your error says "vcom". Is the error from a simulation tool or Quartus?

[Altera_Forum]

Quartus ...

[Altera_Forum]

I've never seen a vcom error in Quartus. I have seen that in ModelSim. Can you print out the whole error message?

[Altera_Forum]

it seems it was an error from ModelSim of Quartus... 

 Is it possible that Quartus's ModelSim (ModelSim AE) doesn't support this syntax while the Quartus itself (compile+filler+placement+...) does support it?   I'm just right away from my PC now...

[Altera_Forum]

It is very possible. Modelsim has much greater 2008 support, but if/else and case generate was oddly one thing they have only more recently supported.

[Altera_Forum]

do you compile with the -2008 flag?

[Altera_Forum]

"do you compile with the -2008 flag?" - yes ....

[Altera_Forum]

Hi, 

 Can you find out which version of ModelSim are you using . The VHDL 2008 syntax is fully supported from the 10.3b release. If you have a pre 10.3b release, it will not support the VHDL2008 full syntax.   -Abr

[Altera_Forum]

I don't know which Modelsim version is bundled with Quartus V16, but V15 comes with 10.3d, so V16 is either the same or newer. 

 Reviewing the previous discussion and misleading reports about a Quartus problem, I'm not sure if dmitryl realizes that Modelsim has it's own VHDL version options, unrelated to the Quartus analysis and synthesis settings.