Variable Frequency of clk

[Altera_Forum]

i have a design that require to run on variable frequency of clk(sampling rate), in the range of 8kHz to 216kHz.  

 My question are: 1. How to write the sdc? 2. Other than sdc, is there any thing(circuit, etc) need to be take care or add in?

[Altera_Forum]

I would expect the "variable frequency" sampling clock implemented as a synchronous clock enable, generated by a clock divider. In this case, no additional timing constraints are involved, because the timing is completey based on the system clock.

[Altera_Forum]

--- Quote Start ---  I would expect the "variable frequency" sampling clock implemented as a synchronous clock enable, generated by a clock divider. In this case, no additional timing constraints are involved, because the timing is completey based on the system clock.  --- Quote End ---   It;s a good idea

[Altera_Forum]

However, my system clk is changing according to n(integer) X fs. Don't you think to add timing constraint?  

 if yes, how?  if no. thanks

[Altera_Forum]

The suggestion is to use a fixed system clock (e.g. 50 MHz) and a variable rate clock enable. The timing requirements don't change with the clock enable rate.

[Altera_Forum]

The system architecture is decided. It is impossible for me to change it.  

 FYI, The system clock is changed on the fly once the user enter through GUI. I think that there is no problem in digital design since it is just connected to the pin of register. Some delay may impact.  The problem is i have no idea to proceed with the Time Quest Analysis without knowing the method to write the sdc file.  Any help will be appreciated.

[Altera_Forum]

Using a divided clock is usually unsuitable, particularly because crossing timing domains can cause timing violations. But if all design logic, except for the clock divider, is run at the divided frequency, in other words, no signal is crossing the timing domains, the analysis is trivial. 

 You may want to start with the classical timing analyser and specify the input frequency to the clock divider. As long as there are no external inputs or outputs, that need to be constrained, this should be sufficient.

[Altera_Forum]

--- Quote Start ---  Using a divided clock is usually unsuitable, particularly because crossing timing domains can cause timing violations. But if all design logic, except for the clock divider, is run at the divided frequency, in other words, no signal is crossing the timing domains, the analysis is trivial.  You may want to start with the classical timing analyser and specify the input frequency to the clock divider. As long as there are no external inputs or outputs, that need to be constrained, this should be sufficient.  --- Quote End ---   http://ifile.it/konx0eg/icao_fpga.schdoc  You can check my design to creat pulse using MAX7000S... Thanks so much

[Altera_Forum]

FvM, 

 Different clock divider will run on different module. So, there are signal across different time domain. In this state, classical timing analysis is still useful for my case?

[Altera_Forum]

--- Quote Start ---  Different clock divider will run on different module  --- Quote End ---   I think, it should handle the internal timing as well. But this fact increases my doubts about your "system architecture" being well considered. (I'm tempted to call it a "no-architecture"). Check the results and be prepared to reconsider the design in time.

[Altera_Forum]

Actually, the pll inside can't handle the the sampling freq, fs like 44.xxxx kHz where the internal PLL(FPGA) can't divide it to the required freq(with fix point) due to limited no. of bits of multiplier and divider(9 bit).  

 In order to fix it, it need a PLL (with more than 9 bit), dsp chip to divide and multiply.  thanks