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Honored Contributor I
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Verify Failed using SDRAM on a DE0 following Altera's tutorial

Hi folks, 

 

I know this has come up countless times - I have read plenty of these threads over the past couple of days. Forewarning that I am very new to FPGA programming/development so I don't have a fantastic base of understanding - meaning that some of the steps I've taken might be horrendously wrong - please point it out if it is. 

 

I am just following the Altera Tutorials (which are outdated by about 4 years) with a DE0 Nano but am trying to run Hello World from the SDRAM not the OnChip memory. The story so far: 

 

I successfully followed the "My First NIOSII for Altera DE-Nano board" tutorial. Part of this involved recognising that the onchip memory wasn't large enough to contain the full C Library (I wanted to use scanf to type into a console which LEDs I wanted to light up). I got it to work using hello_world_small, but I eventually want to use scanf and the likes so I decided to replace the onchip memory with the SDRAM instead to see if I could run it again but with the full Hello World. 

 

I then followed "Using the SDRAM on Altera's DE0 Board with Verilog designs" tutorial which is available on a quick google search. I simply added in the SDRAM and the "System and SDRAM Clocks for DE-series Boards" part which, according to the tutorial, should resolve the timing issues by offsetting the SDRAM's clock. I am 99.9% sure everything is hooked up correctly within QSYS as I have compared the tutorial figures versus my own setup repeatedly.  

 

I then went to my top level verilog module and added in the output "DRAM_CLK", and "passed" (Am I passing it? Not sure on terminology) DRAM_CLK to sdram_clk_clk - which, as far as I can tell, is what they do in the tutorial although they are doing it for some other program lights.v. The tutorial reads "the sdram clock signal sdram_clk generated by the clock signals core connects to the pin dram_clk". I open up pin planner and there is the DRAM_CLK output which I assign as PIN_R4 - as this is where the DE0 Nano user manual says that DRAM_CLK located. Again, I am not sure on whether this is a legitimate step or not - I assume it is because I had to assign the pins when I did the initial Nios II project and did it in a similar manner.  

 

I compile, I load the .sof onto the board, I don't close the time limited warning window, I create the .c/BSP file using the sopcinfo, build and run as Nios II hardware and I get Verify Failed every time. 

 

Any help gratefully received - apologies if my questions/reasoning is bizarre/completely wrong as I have only just started this stuff 

 

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