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Verifying Sampled Data in FPGA ?

Altera_Forum
Honored Contributor II
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Hi, 

 

Is there any way to verify the sampled data in FPGA ? I can see clock and some data in SignalTap but just don't know how to verify if ADC is sampling correctly ? Any way to plot the data inside FPGA or exporting data to text file ? 

 

I really appreciate your help. 

 

Thanks.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

 

Is there any way to verify the sampled data in FPGA ? I can see clock and some data in SignalTap but just don't know how to verify if ADC is sampling correctly ? Any way to plot the data inside FPGA or exporting data to text file ? 

 

I really appreciate your help. 

 

--- Quote End ---  

 

SignalTap II can be accessed from MATLAB, so you can use that to access data captures. 

 

You can also create a design where you capture blocks of data to on-chip RAM or SDRAM, and then read the data capture onto your PC and analyze the data. 

 

Read this DSP tutorial and look at the code; 

 

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104paper_hawkins.pdf 

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104code_hawkins.zip 

 

What board are you using? 

 

Cheers. 

Dave
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