Verilog Coding Help Needed!

[Altera_Forum]

Hi , 

I have Altera Cyclone III board and Quartus II 8.1.  I also have Bitec HSMC DVI daughter board.  My SOPC Design is : DVI_IN => new component => Frame Buffer => DVI_OUT  My goal is to take my DVI display input , XOR it with some random value and output DVI output.   I have the following code which is giving me a black screen. I actually have a more complex version of this code where I try to XOR my input data but seems like I can't pass through data between "data in" and "data out"   Please keep in mind that I did pass through data without using registers but since I also want to do XORing, I try to use the following model.    module new_component (  clk,  data_in,  data_out,  eop_in,  eop_out,  ready_in,  ready_out,  reset,  sop_in,  sop_out,  valid_in,  valid_out  );   input clk;  input [23:0] data_in;  output [23:0] data_out;  input eop_in;  output eop_out;  input ready_in;  output ready_out;  input reset;  input sop_in;  output sop_out;  input valid_in;  output valid_out;      wire clk;  wire [23:0] data_in;  reg [23:0] data_out;  wire eop_in;  reg eop_out;  wire ready_in;  reg ready_out;  wire reset;  wire sop_in;  reg sop_out;  wire valid_in;  reg valid_out;                  always @(posedge clk )  begin   ready_out <= ready_in;  valid_out <= valid_in;  sop_out <= sop_in;  eop_out <= eop_in;  data_out <= data_in;    end endmodule   Please someone help me, this is urgent.   Thank you so much in advance, Tyler