The question is unclear in several regards. I guess, you're talking about frequency multiplication of a clock signal?
If so, it involves a PLL. It's a special FPGA resource, that can't be described in VHDL, but can be instantiated in VHDL user code as a component (MegaFunction). Apart from this standard option, a digital PLL can be designed, but it's output would exist only as a sampled signal, depending on an additional fast clock.
