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Verilog HDL error : cannot connect instance ports both by order and by name

Altera_Forum
Honored Contributor II
‎01-28-2016 01:35 AM
12,990 Views

am doing the SLS SDHC_eMMC card host tutorial 

enclosed in two jpegs are my code. 

http://www.alteraforum.com/forum/attachment.php?attachmentid=11741&stc=1  

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=11742&stc=1
multiple-attachments.zip
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Altera_Forum
Honored Contributor II
‎01-28-2016 08:21 AM
10,314 Views

you forgot the . infront of all port names.

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Altera_Forum
Honored Contributor II
‎01-28-2016 09:57 AM
10,314 Views

You're missing periods ('.') before some of your instantiated module's signal names. 

 

sdhc_conduit_end_SD_CLK (sdc_clk), 

 

should be 

 

.sdhc_conduit_end_SD_CLK (sdc_clk), 

 

Cheers, 

Alex
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Altera_Forum
Honored Contributor II
‎01-28-2016 10:15 AM
10,314 Views

Thanks that was exactly right !

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