Verilog/VHDL versus high level functions.

[Altera_Forum]

Im new to this, coming from audio programming in MSP/Reaktor and lower level assembler. 

So I have to learn a lot about the FPGA stuff as I go along.  But two things came to mind. It was hinted that higher and lower level coding and patching would not make as much of a difference as it does using these in computational languages. Is this so? Can I asume an all code project wether Verilog, VHDL or high level are more or less the same speed and size?  And since im opting to learn one low level language which one should it be? For not running into trouble grabbing MIDI, buffers (RAM), waveform generation, HD's (sata), DAC's, ADC's and the likes..

[Altera_Forum]

--- Quote Start ---  What do you mean by interface node? do you mean a port? and variables are specific things in VHDL - they are different from signals.  Did you mean an intermediate signal?  --- Quote End ---    I mean if you declare the pin in the module description, does this act as a buffer for this number. Or is it needed to re declare variables in code (on the architecture side) even tho these are not used to store any other variable that the one that set the pin to "whatever"?

[Altera_Forum]

Go read a tutorial, find a good boook