Verilog and System Verilog

[Altera_Forum]

I came across that System Verilog is extension of Verilog. Does it mean that Verilog is going to replaced by System Verilog for design since all the original features of Verilog is supported by System Verilog? Thanks

[Altera_Forum]

In my opinion , I dont think so, you need verilog as a basic to move to systemverilog

[Altera_Forum]

Has C++ replaced C? No.

[Altera_Forum]

From your logic can one infer that nothing ever gets replaced by the next generation as long as part of the name is still there :D ?

[Altera_Forum]

Good joke! 

According to my knowledge, C++ is a lexical superset of C that leads to a different method of programming: object-oriented versus procedural. While for some applications object-orientation is the best approach it is not for other applications. So, especially for embedded systems, most developers still use procedural programming, thus C. And I guess they also will use C in the future. The same applies to SystemVerilog. It is a lexical superset for an object-oriented approach on a more abstract level. It will be used for system verification before design but, to my opinion, Verilog-2001 will be the standard for FPGA design for a longer time.

[Altera_Forum]

--- Quote Start ---  Good joke! According to my knowledge, C++ is a lexical superset of C that leads to a different method of programming: object-oriented versus procedural. While for some applications object-orientation is the best approach it is not for other applications. So, especially for embedded systems, most developers still use procedural programming, thus C. And I guess they also will use C in the future. The same applies to SystemVerilog. It is a lexical superset for an object-oriented approach on a more abstract level. It will be used for system verification before design but, to my opinion, Verilog-2001 will be the standard for FPGA design for a longer time.  --- Quote End ---     The point that C is probably here to stay is useful to me, now the next question. How important are function calls in FPGA design? The point being there is some overhead in passing copies of variable/pointers. I realize that if a function is called from many places, there is a saving of memory. Fifty years ago when computers were kids memory was very valuable.   Today it seems that clock frequency and the number of trips through the pipeline/instruction fetches dominates performance limits.   My project is a program that takes C code, generates ram data for a very simple processor that I think will run about as fast as an HDLdesign. I intend to start a thread "CEngine a new kind of embedded processor".  There are other languages but C seems the natural, partly because nearly everyone is familiar.  Thanks, Karl

[Altera_Forum]

SystemVerilog and Verilog do not compare the same as C++ versus C. 

 First off, there is no "performance" degradation using SystemVerilog as is the (arguable) case with C++.  SystemVerilog adds a number of enhancements to Verilog 2001. Some of these are strictly for simulation (such as Classes), while others work for both simulation and synthesis. Much of the synthesis sub-set is supported under Quartus II, and I highly recommend anyone doing *ANY* Verilog to make themselves aware of some of these new capabilities. Some of the ones I feel deserve particular attention are:  1. New data types (logic is my favorite). 2. Enhancements to the port capabilities (can pass 2D arrays) 3. Enumerated types 4. Packages 5. Interfaces  There are more.. but in my opinion the above items are a minimum that any Verilog developer should learn about. I put them in order, not necessarily of importance, but in terms of how easy they are to start using. Interfaces require some rethinking of your code and styles, but I *strongly* believe they are the single most important enhancement (for synthesis).  The only caveat I can think of to using these new capabilities is that Xilinx does not support them... but, of course, that is one great reason to be using Quartus anyway.  (Last I checked Synpicity supports some or all of the above).  Cheers,  Ed