Re: Verilog to VHDL

Altera_Forum · ‎03-06-2013

Hi everyone,

I am having a problem converting a verilog code to vhdl. I know there is a tool does that but it is not working properly. I did write the code in vhdl and the schematic is same. however the output of the two designs are completely different. I have a doubt about the accumulator, could anyone help me figure out what i am doing wrong here.


`timescale 100 ps / 10 ps
`define MSBI 7 // Most significant Bit of DAC input
//This is a Delta-Sigma Digital to Analog Converter
module dac(DACout, DACin, Clk, Reset);
output DACout; // This is the average output that feeds low pass filter
reg DACout; // for optimum performance, ensure that this ff is in IOB
input  DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
reg  DeltaAdder; // Output of Delta adder
reg  SigmaAdder; // Output of Sigma adder
reg  SigmaLatch; // Latches output of Sigma adder
reg  DeltaB; // B input of Delta adder
always @(SigmaLatch) DeltaB = {SigmaLatch, SigmaLatch} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
if(Reset)
begin
SigmaLatch <=# 1 1'b1 << (`MSBI+1);
DACout <=# 1 1'b0;
end
else
begin
SigmaLatch <=# 1 SigmaAdder;
DACout <=# 1 SigmaLatch;
end
end
endmodule


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
&#12288;
entity dac_vhdl is
                port(clk,reset : in std_logic;
                     DAC_in : in std_logic_vector(7 downto 0);
                     DAC_out : out std_logic);
end entity;
architecture beh of dac_vhdl is
signal Adder1_out : std_logic_vector(9 downto 0):=(others=>'0');
signal Adder2_out : std_logic_vector(9 downto 0):=(others=>'0');
signal Latch_out_sig : std_logic_vector(9 downto 0):=(others=>'0');
signal adder1_in : std_logic_vector(9 downto 0):=(others =>'0');
signal Latch_out : std_logic;
&#12288;
begin
Latch_out<= Latch_out_sig(9);
process (Latch_out)
begin
Adder1_in(9 downto 0) <= Latch_out_sig(9)&Latch_out_sig(9)& "00000000";
end process;
process(DAC_in, Adder1_in)
begin
Adder1_out(9 downto 0) <= DAC_in(7 downto 0) + Adder1_in(9 downto 0) ;
end process;
process(Latch_out, Adder1_out)
begin
Adder2_out(9 downto 0) <= Adder1_out(9 downto 0) +  Latch_out_sig(9 downto 0) ;
end process;
process(clk,Reset)
begin
if(Reset='1')then
Latch_out_sig<= "1000000000";
elsif(clk'event and clk='1')then
Latch_out_sig(9 downto 0) <= Adder2_out(9 downto 0);
end if;
end process;
&#12288;
process(clk,Reset)
begin
if(Reset='1')then
DAC_out<='0';
elsif(clk'event and clk='1')then
DAC_out <= Latch_out;
end if;
end process;
end beh;

Altera_Forum · ‎03-06-2013

Both designs are identical, except for one detail. The SigmaLatch initializers have different bit patterns. If you correct the VHDL code respectively, both synthesize to the same gate level code.

SigmaLatch <=# 1 1'b1 << (`MSBI+1);

Sets this bit pattern:

Latch_out_sig<= "0100000000";

If you are referring to X-HDL, it's performing good I think, but needs either well considered rules or some manual rework.

Altera_Forum · ‎03-07-2013

It's a pure simulation issue.

I was only talking about synthesis results and didn't check your code regarding simulation consistency, but I notice that you have wrong sensitivity list entries. Quartus warns about it.