Verilog

[Altera_Forum]

in verilog, how to do like q <= d[count:0]?  

 reg [3:0] count;    thanks

[Altera_Forum]

The expression can't result in a valid syntax, I think. The right-hand-side has a variable length, it can't be assigned to a target with (obviously) fixed length. Furthermore variable ranges are not supported. You should think about an iteration, that copies individual bits.

[Altera_Forum]

You might get a registered mux out of that. Really though I would re-write that as a mux if that was your intent since someone picking up your source file might struggle to figure out what it's supposed to do.

[Altera_Forum]

Fvm, 

 i have tried on iteration but all fails. do you any simple example on iteration for my case?

[Altera_Forum]

I didn't understand your intention yet. Do you mean to select a single bit? [count:0] is a range rather than a bit. Please clarify also the type of the other involved signals.

[Altera_Forum]

My intention is same as to select range of bits. From your previous post, you suggest me to do iteration to achieve my intention. However, i fail to do it using for loop. That's why asking for some example.

[Altera_Forum]

O.K., select a range of bits. But you can't assign a variable length selection range to a fixed length target. So again, what's the type of involved signals and what kind of assignment is intended for it.

[Altera_Forum]

the count(reg) is dependent on input while q is output. it is non blocking assignment. Does blocking or non blocking play an important role in it? 

 thanks

[Altera_Forum]

--- Quote Start ---  Does blocking or non blocking play an important role in it?  --- Quote End ---   Not in this case, I think. What is the bitwidth of d and q?

[Altera_Forum]

Both of it also 32bit.

[Altera_Forum]

module test ( input d, input count, output reg q ); integer i; always @(*) begin for (i=0;i<=count;i=i+1) q <= d; end endmodule

[Altera_Forum]

thanks. it is very simple and helps me

[Altera_Forum]

hello . 

am running verilog code and the same error keep showing up ,    errors : Error (10028): Can't resolve multiple constant drivers for net "hazard" at design1.v(159) Error (10029): Constant driver at design1.v(138) Error (10028): Can't resolve multiple constant drivers for net "sample" at design1.v(159) Error: Can't elaborate top-level user hierarchy Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 5 warnings Error: Peak virtual memory: 181 megabytes Error: Processing ended: Tue Apr 20 13:20:20 2010 Error: Elapsed time: 00:00:02 Error: Total CPU time (on all processors): 00:00:01 Error: Quartus II Full Compilation was unsuccessful. 6 errors, 5 warningshttp://www.alteraforum.com/forum//proweb/misc/progress.gif    this is the code ;  module design1 ( clock ,  reset ,  hazard , pulse  ); // End of port list //-------------Input Ports----------------------------- input clock ; input reset ; input pulse ; //-------------Output Ports---------------------------- output hazard ; //-------------Input ports Data Type------------------- // By rule all the input ports should be wires  wire clock ; wire reset ; //-------------Output Ports Data Type------------------ // Output port can be a storage element (reg) or a wire reg [15:0] pulse_cntr; reg pulse_reset; reg [15:0] period_cntr;  reg [15:0] sample_value; reg sample;   reg [23:0] result, result_ns; reg [23:0] vt; reg hazard;  initial begin hazard = 1'b0 ; end  always @ ( sample_value ) begin  result_ns = sample_value * 4'hc; case ( result )  24'h00006c: vt = 24'hcccccc; 24'h0186A0: vt = 24'h007530; 24'h030D40: vt = 24'h00EA60; 24'h0493E0: vt = 24'h01ADB0; 24'h061A80: vt = 24'h020F58; 24'h07A120: vt = 24'h029810; 24'h0927C0: vt = 24'h030D20; 24'h0AAE60: vt = 24'h038270; 24'h0C3500: vt = 24'h041EB0; 24'h0DBBA0: vt = 24'h04BAF0; 24'h0F4240: vt = 24'h053020; 24'h10C8E0: vt = 24'h05CC60; 24'h124F80: vt = 24'h064190; 24'h13D620: vt = 24'h0704E0; 24'h155CC0: vt = 24'h077A10; 24'h16E360: vt = 24'h07EF40; 24'h186A00: vt = 24'h086470; 24'h19F0A0: vt = 24'h0927C0; 24'h1B7740: vt = 24'h099CF0; 24'h1CFDE0: vt = 24'h0A6040; 24'h1E8480: vt = 24'h0AFC80; 24'h200B20: vt = 24'h0B4AA0; 24'h2191C0: vt = 24'h0C0DF0; 24'h231860: vt = 24'h0CAA30; 24'h249F00: vt = 24'h0D1F60; 24'h2625A0: vt = 24'h0DE2B0; 24'h27AC40: vt = 24'h0EF7E0; 24'h2932E0: vt = 24'h0EF420; 24'h2AB980: vt = 24'h0F9060; 24'h2C4020: vt = 24'h102CA0; 24'h2DC6C0: vt = 24'h10EFF0; 24'h2F4D60: vt = 24'h116F20; 24'h30D400: vt = 24'h120160; 24'h325AA0: vt = 24'h12C4B0; 24'h33E140: vt = 24'h1360F0; 24'h3567E0: vt = 24'h13D620; 24'h36EE80: vt = 24'h149970; 24'h387520: vt = 24'h1535B0; 24'h39FBC0: vt = 24'h15D1F0; 24'h3B8260: vt = 24'h169540; 24'h3D0900: vt = 24'h1731A0; 24'h3E8F9F: vt = 24'h17A6B0; 24'h401640: vt = 24'h1842F0; 24'h419CE0: vt = 24'h190640; 24'h43237F: vt = 24'h19A280; 24'h44AA20: vt = 24'h1A65D0; 24'h4630C0: vt = 24'h1ADB00; 24'h47B760: vt = 24'h1B7740; 24'h493E00: vt = 24'h1C3A90; 24'h4AC4A0: vt = 24'h1CD6D0; 24'h4C4B40: vt = 24'h1D7310; 24'h4DD1E0: vt = 24'h1E3660; 24'h4F5880: vt = 24'h1ED2A0; 24'h50DF20: vt = 24'h1F95EF; 24'h5265C0: vt = 24'h203230; 24'h53EC60: vt = 24'h20A760; 24'h557300: vt = 24'h2191C0; 24'h56F9A0: vt = 24'h222E00; 24'h588040: vt = 24'h22F150; 24'h5A06E0: vt = 24'h238D90; 24'h5B8D80: vt = 24'h2450E0; 24'h5D1420: vt = 24'h243610; 24'h5E9AC0: vt = 24'h258960; 24'h602160: vt = 24'h264CB0; 24'h61A800: vt = 24'h271000; 24'h632EA0: vt = 24'h27AC40; 24'h64B540: vt = 24'h282170; 24'h663BE0: vt = 24'h290BD0; 24'h67C280: vt = 24'h29CF20; 24'h694920: vt = 24'h2A6B60; 24'h6ACFC0: vt = 24'h2B07A0; 24'h6C5660: vt = 24'h2BCAF0; 24'h6DDD00: vt = 24'h2CB550; 24'h6F63A0: vt = 24'h2D5190; 24'h70EA40: vt = 24'h2F4D60; 24'h7270E0: vt = 24'h2EB120; 24'h73F780: vt = 24'h2F7470; 24'h757E20: vt = 24'h2FE9A0; 24'h7704C0: vt = 24'h30ACF0; 24'h788B60: vt = 24'h317040; 24'h7A1200: vt = 24'h320C80; default : vt = 24'h0000;  endcase if ( result_ns <= vt )  hazard = 1; else hazard = 0;  end   // Pulse Counter always @(posedge pulse or posedge reset) begin  if ( reset == 1'b1 ) begin sample_value <= 0; pulse_cntr <=0; hazard = 0 ; end else if (sample == 1) begin sample_value <= pulse_cntr+1; pulse_cntr <= 0; sample <= 0;  end else  begin pulse_cntr <= pulse_cntr + 1; end end  // Period counter always @(posedge clock or posedge reset) begin  if (reset == 1'b1) begin period_cntr <= 0; sample <= 0; hazard = 0 ; end else if ( period_cntr == 16'h000f)//557300  begin period_cntr <= 16'h0000; sample <= 1;  end else  begin period_cntr <= period_cntr + 1; end end     always @(posedge clock or posedge reset) begin  if (reset == 1'b1)// begin  result <= 0;  else  result <= result_ns ;  end   endmodule // End of Module design

[Altera_Forum]

The error message means that you are not allowed to use your output hazard in more than one always block.There´s the same problem with your reg sample. Try to fix that first, maybe there are some more problems.

[Altera_Forum]

Please do not multipost your question