I'm using a Cyclone IV E series FPGA connecting to a Mux/Demux chip. Both of them will be configured as LVDS interface. Since I didn't find clear description about common mode voltage (Vicm and Vos) of LVDS interface from cyclone IV handbook and datasheet, only electrical characteristcs were mentioned. All of the LVDS interfaces were assigned on Row I/O banks (using true LVDS buffer). My questions are:
1. For Cyclone IV E LVDS receivers , I can make sure it need external termination resistor, but if they have internal biased voltage？I'd like to choose DC coupling for this side signals (Vicm and Vid ranges of Cyclone LVDS receiver are very big)
2. For Cyclone IV E LVDS transmitters, whether they were internally biased or not? if the MUx chip has a internal biased voltage, what's the effect to FPGA LVDS transmitter by DC coupling? (Vos of Cyclone IV LVDS is 1.125V~1.375V, while Vicm of Mux chip LVDs is 0.875V~1.52V). I'd like to use AC coupling for this side to get high reliability, but I don't know if I need to externally bias for Cyclone LVDS transmitter.
