Video designed with openLDI_TX degraded after power cycle

[Mingyuexin]

Hi, 

I'm working on a customer board where we use OpenLDI module I found here (https://community.intel.com/t5/FPGA-Wiki/IP-Component-OpenLDI-FPD-Link-Camera-Link-VIP-Component-for-Qsys/ta-p/735654) to drive our video display through lvds interface. The format of  video/pictures is RGB, each color has 8 bits. 
It works fine during test, but we found out the video/picture is degraded after power cycle. 

There would be unneeded line in the picture. 

I do not have not clew, so I would like to check the timing constraint for OpenLDI. It seems I do not have control of the timing constraints of OpenLDI module. Does anybody know how and where I can check the timing of this module? 

Any suggestion about debugging this issue?

Any reply is appreciated. 

Thank you very much in advance!

Mingyuexin

[ZH_Intel]

Hi Mingyuexin,

Thank you for reaching out.

Apologize for the delayed response as we encounter some technical difficulty.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZH_Intel

[Mingyuexin]

Hi,

Thank you very much for the response. 

I found that resetting CVO and OpenLDI would remove the issue. 

So I'm afraid there is timing issue between OpenLDI and the receiver chip on the board. 

OpenLDI utilize altlvds_tx to convert parallel data to serial data. Since it's a hardcore ip (SERDES), so I did not set any output timing constraint for the pins. So if timing constraint on the output pins are necessary, how to set then? There is no timing data from the datasheet of the receiver chip on the board either. 

Thank you very much for your time!

With best wishes

Mingyuexin 

[ZH_Intel]

Hi Mingyuexin,

Apologize for the delayed response.

Thank you for your reply.

Regarding timing constrain, you may refer to I/O constrain in the Timing Analyzer Cookbook.

This document contains a collection of design scenarios, timing constraint guidelines, and techniques that you can apply to help optimize timing performance of your FPGA device.

You may refer to below documents for more information:

1. Intel® Quartus® Prime Timing Analyzer Cookbook
2. OpenLDI Interface Blocks for Qsys 
3. Timing Analyzer Resource Center 

We also have a demo design for OpenLDI. Please do note that this design is for demonstration purpose so they might have no timing constrains for the I/O.

For custom design, you may need to add the IO timing constrains for the I/O pins.

- OpenLDI TX/RX Built-In Self Test (BIST) Design Example

Hope this answers your question.

Thank you. 

Best Regards,

ZH_Intel

[ZH_Intel]

Hi Mingyuexin,

Good day.

Hope my previous reply answers your question.

Do you still have further inquiries on this issue?

If there is no further inquiries, I will transition this thread to community support. 

Thank you. 

Best Regards,

ZH_Intel

[ZH_Intel]

Hi Mingyuexin,

Good day.

We do not receive any response from you to the previous reply that I have provided. 

Since there is no further inquiries, this thread will now be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Stay safe, and I hope you have a great day.

Thank you. 

Best Regards,

ZH_Intel