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before i begin let me explain that in the last post i made i had a problem deciding whether to assign a sdram pin known as SDRAM_CKE ... in the tutorial i am using in the top level entity file it is established but not assigned to a wire. for example
In the outdated tutorial .sdram_wire_cke is defined as .sdram_wire_cke ( ), so it is declared it using a more modern tutorial for the BEMICROMAX 10 i found that it is declared .sdram_cke (SDRAM_CKE), // .cke so this is programmed in and saved.... but when i try to start analysis and elaboration it goes all the way through but gives me an warning Warning (10236): Verilog HDL Implicit Net warning at cc_r2a_refdes_sdhc_cntrl.v(40): created implicit net for "sdr_cke" for the sdram_cke on this line and there is no sdram_cke in the pin planner... am i missing a step ?Link Copied
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Have you got an input or output declared on your top level module Verilog file with the name SDRAM_CKE?
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ok, smart thinking ! i looked and CKE should be an output
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ok now it shows up in pin planner thanks !
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