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NShan12
New Contributor I
536 Views

Warning: Node: WRN was determined to be a clock but was found without an associated clock assignment.

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Hello, I have a input signal WRN (Write enable) driven by microcontroller. I use WRN's rising edge to read the data on the bus. The code fragment is:

 

IF ( WRN'event AND WRN= '1' ) THEN 

datum <= adbus( 15 DOWNTO 0 );

 

Now, during compilation I get the warning "WRN was determined to be a clock but was found without an associated clock assignment" and the fitter reports "Design is too large" error.

 

please suggest how should I constrain the WRN signal in the SDC file to avoid the warning for a successful compilation. Thank you!

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1 Solution
NShan12
New Contributor I
220 Views

Update:

 

I created a rising edge detector signal 'WRN_re'

 

WRN_re <= (WRN_d XOR WRN) AND WRN; -- WRN_d is the delayed version of WRN (generated from a clocked process)

I used this signal to read data from the bus instead. The warning still exists. After checking the RTL viewer, I clearly see that WRN is never connected to clock pin of any flip flop.

Now I do not understand why the comiler is considering WRN as a clock and throwing the warning.

 

Also the new error pops up:

 

Error (332000): Following required options are missing: -clock

---------------------------------------------------------------------------

Usage: set_input_delay [-h | -help] [-long_help] [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>

 

    -h | -help: Short help

    -long_help: Long help with examples and possible return values

 

    -add_delay: Create additional delay constraint instead of overriding previous constraints

    -clock <name>: Clock name

    -clock_fall: Specifies that input delay is relative to the falling edge of the clock

    -fall: Specifies the falling input delay at the port

    -max: Applies value as maximum data arrival time

    -min: Applies value as minimum data arrival time

    -reference_pin <name>: Specifies a port in the design to which the input delay is relative

    -rise: Specifies the rising input delay at the port

    -source_latency_included: Specifies that input delay includes added source latency

    <delay>: Time value

    <targets>: List of input port type objects

---------------------------------------------------------------------------

  while executing

"set_input_delay –clock CONTCLK_IN 5 [get_ports WRN]"

 

The command in bold is the SDC command I have used for WRN. Is the syntax of the SDC command right? I followed the Quartus tutorial to write this command.

 

Requesting your help. Thank you in advance!

View solution in original post

18 Replies
sstrell
Honored Contributor II
220 Views

You've written this code such that WRN looks like a clock instead of an enable. You should have something like this:

 

process (clk)

begin

if rising_edge(clk) then

if WRN='1' then

datum <= adbus(15 downto 0);

 

Then of course you need an SDC constraint for clk. WRN would have a set_input_delay constraint.

 

As for why you're getting a no fit error, it most likely would not be because of this issue, which is just a warning. Something else is using up resources in your design.

 

#iwork4intel

NShan12
New Contributor I
220 Views

Hello sstrell,

 

Thank you for your reply.

 

This is an asynchronous interface between Microcontroller and FPGA. The FPGA waits for WRN's rising edge and then reads the data on bus. Since there is no clock involved, I cannot modify the code as per your suggestion.

Is there any other way you think to solve this?

 

One hint: I will check if I can proceed with reading data when WRN = '0' instead? This wouldnt confuse the compiler about WRN.

 

I will look into the fitter error, no need to worry about that now.

NShan12
New Contributor I
221 Views

Update:

 

I created a rising edge detector signal 'WRN_re'

 

WRN_re <= (WRN_d XOR WRN) AND WRN; -- WRN_d is the delayed version of WRN (generated from a clocked process)

I used this signal to read data from the bus instead. The warning still exists. After checking the RTL viewer, I clearly see that WRN is never connected to clock pin of any flip flop.

Now I do not understand why the comiler is considering WRN as a clock and throwing the warning.

 

Also the new error pops up:

 

Error (332000): Following required options are missing: -clock

---------------------------------------------------------------------------

Usage: set_input_delay [-h | -help] [-long_help] [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>

 

    -h | -help: Short help

    -long_help: Long help with examples and possible return values

 

    -add_delay: Create additional delay constraint instead of overriding previous constraints

    -clock <name>: Clock name

    -clock_fall: Specifies that input delay is relative to the falling edge of the clock

    -fall: Specifies the falling input delay at the port

    -max: Applies value as maximum data arrival time

    -min: Applies value as minimum data arrival time

    -reference_pin <name>: Specifies a port in the design to which the input delay is relative

    -rise: Specifies the rising input delay at the port

    -source_latency_included: Specifies that input delay includes added source latency

    <delay>: Time value

    <targets>: List of input port type objects

---------------------------------------------------------------------------

  while executing

"set_input_delay –clock CONTCLK_IN 5 [get_ports WRN]"

 

The command in bold is the SDC command I have used for WRN. Is the syntax of the SDC command right? I followed the Quartus tutorial to write this command.

 

Requesting your help. Thank you in advance!

View solution in original post

sstrell
Honored Contributor II
220 Views

Then your code is correct and you should false path the WRN input. It's not a good idea to have a truly asynchronous input like this, especially a control signal. You might want to consider synchronizing WRN in the FPGA with a clock through a synchronizer chain of registers.

 

Is there a PROCESS statement above the code you've posted?

 

#iwork4intel

NShan12
New Contributor I
220 Views

Sure sstrell, I will add multiple registers as synchronizers for WRN.

 

YES. There is a PROCESS statement to derive the rising edge signal.

 

edge: PROCESS (contclk, dff_clearn)            

BEGIN

IF dff_clearn = '0' THEN

wrn_d <= '0' ;

ELSIF contclk'EVENT AND contclk= '1' THEN

 wrn_d <= wrn;

END IF;

END PROCESS;

 

Also please comment on the syntax of "set_input_delay" SDC command. Im getting an error as explained in earlier post.

 

 

sstrell
Honored Contributor II
220 Views

WRN is asynchronous, so you can't use set_input_delay with it. You have to false path it.

#iwork4intel

NShan12
New Contributor I
220 Views

Thank you. The false path is set for all bus signals that are asynchronous. Synchronizer registers are added before reading the data from the bus.

Seems good for now and the compilation is through.

 

NShan12
New Contributor I
220 Views

Hello,

 

Following up on this, should all the asynchronous inputs to the pins of FPGA shall be considered false paths? and hence no input constraints can be applied to them?

I would like to know how to treat the synchronous outputs of FPGA, that are read asynchronously by the microcontroller. Should these FPGA outputs be constrained with output delays?

 

The unconstrained paths report from timing analyser after compilation shows the below results. Kindly let me know how can I completely constrain my design.

 

Property Setup Hold

Illegal Clocks 0 0

Unconstrained Clocks 2 2

Unconstrained Input Ports 60 60

Unconstrained Input Port Paths 2570 2570

Unconstrained Output Ports 88 88

Unconstrained Output Port Paths 1305 1305

 

Thank you again!

sstrell
Honored Contributor II
220 Views

Should all the asynchronous inputs to the pins of FPGA shall be considered false paths? Yes. If they are not launched by a clocked device (that clock is a virtual clock that you need to constrain, by the way), they are asynchronous and can't use set_input_delay. And set_input_delay always uses the external clock (the virtual clock) for the -clock argument to define the launch edge for the input analysis.

 

Should these FPGA outputs be constrained with output delays? If they are latched by the downstream device by a clock (another virtual clock), then again you use set_output_delay. If not, you could just false path them.

 

Can you indicate what paths are being considered clock and I/O paths that need to be constrained? Can you post your .sdc?

 

#iwork4intel

NShan12
New Contributor I
220 Views

Hello sstrell,

 

Please find the IO interface in my top level module:

 

Synchronous IO:

 

i_contclk : IN STD_LOGIC; --32Mhz main clock

i_clk1 : IN STD_LOGIC; -- dedicated clock for speecial application 1, derived from external oscillator

i_clk2 : IN STD_LOGIC; -- dedicated clock for speecial application 2 derived from external oscillator

i_clk3 : IN STD_LOGIC; -- dedicated clock for speecial application 3 derived from external oscillator

i_clk4 : IN STD_LOGIC; -- dedicated clock for speecial application 4 derived from external oscillator

 

 

o_int : OUT STD_LOGIC; -- Interrupt signal from FPGA to Microcontroller

 

o_sts : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); --Enable signals for external multiplexer switch IC

CM : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- feedback from the above multiplexer IC. I dont know if this is synchronous input. Mux doesnt has any clocks connected to it.

o_watchdog : OUT STD_LOGIC; -- Time-out signal of Watchdog to Microcontroller

o_WR_n : OUT STD_LOGIC; --Write Enable to external ASIC

o_RD_n : OUT STD_LOGIC; --Read Enable to external ASIC

o_CEPROM : OUT STD_LOGIC; --EEPROM Enable

o_abt : OUT STD_LOGIC; --Sampling signal to ADC from FPGA

 

 

Asynchronous IO:

 

TOUT : IN STD_LOGIC; -- Data Request Signal from external system. This system is placed far from my FPGA board

EXTCLR : IN STD_LOGIC; -- Reset input from a push button

DISCR_IN : IN STD_LOGIC_VECTOR (15 DOWNTO 0); -- Asynchronous discrete inputs

-- BUS signals to communicate with Microcontroller (All Asynchronous)

AD : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);

ALE : IN STD_LOGIC;

CLEARN : IN STD_LOGIC;

WRN : IN STD_LOGIC;

RDN : IN STD_LOGIC;

--ADC Signal

FLASH :IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from ADC. Is this considered synchronous? FPGA supplies control signals to ADC from clocked processes and we know the time within which the ADC provides data on its pins

--DAC Signal( All synchronous)

 o_dac_clk : OUT STD_LOGIC; -- clock supplied to DAC

o_DAC_data : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); -- Data supplied to DAC 

 

 

Here are the .sdc file commands:

 

create_clock -name { i_contclk} -period 31.25 -waveform { 0.000 15.625 } [get_ports { i_contclk}]

create_clock -name {i_clk1} -period 31.25 -waveform { 0.000 15.625 } [get_ports{ i_clk1}]

create_clock -name {i_clk2} -period 31.25 -waveform { 0.000 15.625 } [get_ports {i_clk2}]

create_clock -name {i_clk3} -period 31.25 -waveform { 0.000 15.625 } [get_ports {i_clk3}]

create_clock -name {i_clk4} -period 31.25 -waveform { 0.000 15.625 } [get_ports {i_clk4}]

 

set_false_path -from [get_pins i_contclk] -to [get_pins WRN]

set_false_path -from [get_pins i_contclk] -to [get_pins ALE]

set_false_path -from [get_pins i_contclk] -to [get_pins RDN]

set_false_path -from [get_pins i_contclk] -to [get_pins CLEARN]

set_false_path -from [get_pins i_contclk] -to [get_pins AD]

 

Really appreciate for taking time to look into this.

 

After reading your comments, my next steps are:

Almost all the inputs are asynchronous, so I will false path them. Please let me know if I should consider the external oscillator clocks as synchronous or asynchronous.

 

I will create virtual clocks based on the devices latching the synchronous data from FPGA. I would like to know how to calculate the delay value in set_output_delay command.

sstrell
Honored Contributor II
220 Views

So which paths is the timing analyzer showing as unconstrained clocks?

 

You need false paths or set_input[output]_delay on all I/O to fully constrain the design.

 

If you are outputting a clock (why do you say it's asynchronous?), that's basically a source synchronous interface. You need to create a generated clock constraint on the output port.

 

There is a lot going on here. I highly recommend you check out the timing analyzer online trainings, especially "Required SDC constraints":

 

https://www.intel.com/content/www/us/en/programmable/support/training/catalog.html?courseType=Online...

 

#iwork4intel

NShan12
New Contributor I
220 Views

Hello sstrell,

 

ALE and WRN were shown as unconstrained clocks since these were directly connected to clock pin of FF. The rising and falling edges of these were used to latch the data. Now its no more shown as unconstrained, since I used an edge detection signal and then latching the data.

 

You need false paths or set_input[output]_delay on all I/O to fully constrain the design. - Yes, I will make sure this is done.

 

You need to create a generated clock constraint on the output port. - Absolutely, this was somewhere down in the mind but I can say, I never understood the real meaning of this. It makes sense now, I will use this command.

 

Thank you for the link! I will go through all the trainings and work it out. 😄

KennyT_Intel
Moderator
220 Views

Hi,

 

Just to make some corrections:

 

You need false paths or set_input[output]_delay on all I/O to fully constrain the design. - Yes, I will make sure this is do

 

You cannot simple false path the input delay. As this need to be analyze. You can set input delay on it. Analyze those path in timing analyzer to see if you can close those timing.

 

Set input delay had to be associated with a clock. You need to understand where does those port connected to the external device. Those port must have associated with a clock inside the fpga or outside the fpga(virtual clock)

 

You need to create a generated clock constraint on the output port.

To explain this, this is used usually if you have a PLL/any clock that is connected to the output port. This usually will be use together with your set-input-delay or output-delay. Depending on your design on how you would like to associate the clock with it.

NShan12
New Contributor I
220 Views

Hello kTan_Intel,

 

I have used both set_input_delay and set_false_path command after analyzing the input paths from the Bus interface and ADC to the FPGA.

 

Regarding the generated clocks, In case of DAC interface, clock to DAC is derived from main clock and is connected to output port.

 

In ADC interface: I have a pulse signal triggered in a state machine that sends sample command to ADC (to sample data at 2MHz). This can be considered clock, but I am not sure if it actually is a clock. Can I use similar generated clock command for the pulse signal too

 

KennyT_Intel
Moderator
220 Views

Alright, I just want to let you know if you set set_false_path. Quartus will stop analyze those path and you have to be careful on using those. Make sure your analysis is correct when you use this command.

NShan12
New Contributor I
220 Views

Yes. Understood. I would like to have your comments on the pulse signal. Any ideas on how this signal can be constrained?

Thank you in advance.

NShan12
New Contributor I
220 Views
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