HelloI've been investigating the watchdog functions on the Cyclone V SoC and have found that although the "l4wd1" watchdog appears to be working, the "l4wd0" does not. I have set the wdt_torr first to be various values, 0xCC gives a 13s initial timeout and 13s restart timeout. I then set the wdt_cr register to 0x1 to enable the wdog. As I mentioned, l4wd1 seems to correctly reset the HPS on a timeout, whereas l4wd0 never times out... When I read the current timer value, the top byte is always 0x7F, which leads me to believe that the timer is not working correctly. Some further investigation shows that the l4wd0 will time out for values less than 0x7 on the timeout register, which doesn't load the top byte, the reset happens as expected. Is this a known issue with the silicon? Regards Dave
I observed the same behavior. watchdog 0 (l4wd0) does not behave correctly when using counter values above 0x7. With large counter values, the count did appear to be decrementing, but very slowly (about 10x slower than expected). Also writing 0x76 to the restart register did not appear to restart the counter. I gave up and used l4wd1 which seems to work fine. Is there any explanation from Altera?