Weak pullup during MAX10 FPGA configuration

[Vijayn]

Hi,

In my custom board with MAX10 FPGA mounted, after power-on the board, there is a 700mV seen on the pin J1 DIFFIO_RX_L19n for around 5 milli second. I understood that this due to the weakpull-up enabled during FPGA configuration (during READ ICB setting stage). Please correct if this understanding is wrong.

If it is correct, please let me know how to disable this weakpullup at all stages of FPGA configuration until it reaches user mode.

Vijay

[YuanLi_S_Intel]

Hi,

Apologize that the weak pull up cannot be disabled during Read ICB Settings.

Thank You