What are the differences between Altera & Xilinx Deserialization?

[Altera_Forum]

What are the differences between Altera & Xilinx Deserialization? anybody knows? 

 Xilinx released several application notes, e.g." Connecting Xilinx FPGAs to Texas Instruments ADS527x Series ADCs", "An Interface for Texas Instruments Analog-to-Digital Converters with Serial LVDS Outputs", Xilinx doesn't have a Megafunction as "ALTVLDS".  while Altera released "ALTLVDS Megafunction User Guide", "Design Example Using the altlvds Megafunction & the External PLL Option in Stratix II Devices"  Altera mainly uses "ALTPLL" "ALTLVDS" megafunction, are they simpler than xilinx design? are the blocks in Xilinx design, e.g. "Bit Swap Multiplexer" still needed in Altera design? or they are included in ALTLVDS megafunction:confused:?  Thank you very much!

[Altera_Forum]

What device and speed are you running at? 

In general, use Altera't True LVDS I/O when possible. This is pretty close to dedicated silicon for running high-speed interfaces. TimeQuest will report an RSKM value, which you need to determine if it's fast enough for your system. If you want a really fast receiver(up to 1.6 Gbps), then you'll need DPA. Probably the biggest downside to Altera's solution is that it's not as flexible, being dedicated silicon. For example, you may not have enough I/Os. Or you may run out of PLLs(although DPA can help with this too.) Xilinx has some dedicated features in each I/O, which tends to make their solution more flexible. It's basically a calibrated delay chain and serdes function. The downside is that for higher clock rates, it takes logic to control all this. Look at their real-time window monitoring.  For the most part, you should be able to do anything in both architectures, so I wouldn't worry so much about comparing the two.

[Altera_Forum]

I am trying to deserialize Texas Instruments ADCs, there are not much information in Altera application notes. The Xilinx application notes is much more detailed, however I sitll do not know how to transplant these designs to altera devices.

[Altera_Forum]

What speed and device? In general, put down and altlvds block and you should be good to go. If you needed really high-speeds, you would want to enable DPA, but I doubt that's what you're doing, since you'd be using the real-time window monitoring in X.

[Altera_Forum]

I don't need very high speed, I need to deserialize ADC converstion from Texas Instruments ADCs. Most of them are 40MSPS*14bits.  

 What puzzles me mostly are the details. For example, ALTLVDS RX seems only need one input clock (AD clock), it generate bit clock using PLL, while Xilinx design uses two input clocks, need AD clock and bit clock from the ADC chip.   Xilinx design need "Bit Swap Multiplexer" and a lot of components,  but Altera design seems only need ALTLVDS_RX. Does Altera design need those components?

[Altera_Forum]

Only one clock is necessary, as PLL does the rest. Technically you should be able to do everythign with the altlvds block. I don't know enough about the bit swap mux, but would be surprised if it were necessary. The data should come out in parallel to your data clock rate. If the order is incorrect, you just switch the hookup. I'm not sure what they're changing on the fly.

[Altera_Forum]

With Altera Cyclone family the DESER function is implemented ín logic as well and they have no DPA available. Starting with Cyclone III, PLL dynamic phase shift could be used as a DPA replacement, but I didn't yet need it for similar applications. I assume, that your ADC application has bit rates up to 600 or 700 MBPS, it it could basically work e.g. with Cyclone III and fixed receive phase. 

 You can get a bit swap issue, if dynamical phase align operation crosses a word boundary. For the said speed range, I prefer to adjust the receiver PLL phase manually to center of the receive window, the PLL is clocked by the ADC FCO.

[Altera_Forum]

I don't understand why only need one clock in Altera? 

 The ADCs has both AD clock and bit clock output, so how to do with the bit clock output in Altera?     --- Quote Start ---  Only one clock is necessary, as PLL does the rest. Technically you should be able to do everythign with the altlvds block. I don't know enough about the bit swap mux, but would be surprised if it were necessary. The data should come out in parallel to your data clock rate. If the order is incorrect, you just switch the hookup. I'm not sure what they're changing on the fly.  --- Quote End ---  

[Altera_Forum]

If you use a PLL for the LVDS reveiver, the bit clock (fast clock) is generated from the FCO by frequency multiplication automaticly. You don't have an option to use a different bit clock in this case. 

 With Cyclone family, that has no dedicated DESER circuit, you're basically able to save the receiver PLL and supply SERDES frame and bit clock from the ADC. But you loose the option to adjust the receiver phase for maximum RSKM (receiver input skew margin). I didn't yet try this design variant, it may be necessary for a Cyclone design that runs short of PLLs.

[Altera_Forum]

So the LVDS receiver will automatically adjust the receiver phase for maximum RSKM if use a PLL? 

 Isn't the ALTLVDS_Rx megafunction a dedicated DESER circuit in Cyclone?  In Xilinx design, the SERDES frame and bit clock go through a DCM (http://www.google.com.hk/url?q=http://www.xilinx.com/support/documentation/ip_documentation/dcm_module.pdf&sa=x&ei=jffhs-vghc-tkaxxwrm9cq&ved=0cagqzgqoadaa&usg=afqjcnhi23tc7buynxnz1e16-128gobl3g)(Digital Clock Manager) to align receiver phase, it is not used directly.     --- Quote Start ---  If you use a PLL for the LVDS reveiver, the bit clock (fast clock) is generated from the FCO by frequency multiplication automaticly. You don't have an option to use a different bit clock in this case.  With Cyclone family, that has no dedicated DESER circuit, you're basically able to save the receiver PLL and supply SERDES frame and bit clock from the ADC. But you loose the option to adjust the receiver phase for maximum RSKM (receiver input skew margin). I didn't yet try this design variant, it may be necessary for a Cyclone design that runs short of PLLs.  --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  Isn't the ALTLVDS_Rx megafunction a dedicated DESER circuit in Cyclone?  --- Quote End ---    No, not in Cyclone.    --- Quote Start ---  So the LVDS receiver will automatically adjust the receiver phase for maximum RSKM if use a PLL?  --- Quote End ---    Only on families that support DPA (Stratix II-IV, Arria I-II). Not in Cyclone I-IV and other families.     --- Quote Start ---  In Xilinx design, the SERDES frame and bit clock go through a DCM (Digital Clock Manager) to align receiver phase, it is not used directly.  --- Quote End ---  In Altera you have two options  a) use the frame and bit clock directly.  You won't be be able to have any control over phase, so it's not very recommendable.  b) generate the bit clock from the frame clock using a PLL. In a device that supports DPA, the altlvds_rx function will be able to automatically adjust the bit clock's phase to maximize RSKM. On the ones that don't support DPA, it won't. But in PCB, where delays are more or less stable, you can manually tune the PLL's output phase to get a good RSKM.