Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18980 Discussions

What does usedw count in FIFO that has different input and output widths?

Altera_Forum
Honored Contributor II
914 Views

It is possible to have DCFIFO that has 16 bit input port and 32 bit output port and also reverse! 

What does the usedw signal count in these scenarios? Does it count how many 16 bit words it has stored or how many 32 bit words it has stored?
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
113 Views

The SCFIFO core doesn't support mixed width as far as I can tell.  

 

The DCFIFO does however, but that has separate read and write used word signals (wrusedw and rdusedw). So they will represent the width of the respective ports.
Altera_Forum
Honored Contributor II
113 Views

Sorry, I corrected the question. You have answered the question. Basically, in the code I was looking at, at top level there was just one usedw signal and not two. However, looking deaper into the code I have found that a DCFIFO is being used and one of the usedw is not connected to the module port.

Reply