Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

What is the Top-Level Design

Altera_Forum
Honored Contributor II
‎02-17-2012 07:31 PM
1,176 Views

What is the content of this exactly! :(

0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎02-17-2012 08:44 PM
458 Views

the top level is the module that defines the I/O of the FPGA to the outside work, and instantiates the logic used in the design

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.