Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19088 Discussions

What is the highest data rate with Cyclone 10 GX pins in diff SSTL 1.2 V?

Twincreeks
Beginner
310 Views
 

I hope to use a Cyclone 10 GX device to transmit data. The datasheet specifies the highest data rate to be 1.434 Gbps. It is not an issue for LVDS standard with the LVDS SERDES IP, but I need to use diff SSTL-12 because the common-mode voltage of LVDS is incompatible with my receiver. Can I transmit data at 1.434 in diff SSTL-12? If yes, how should I do? Is there other SERDES IP that supports SSTL? If not, what is the highest data rate that diff SSTL-12 can achieve? Thanks.  

0 Kudos
1 Solution
EngWei_O_Intel
Employee
282 Views

Hi Twincreeks

 

This is the understanding we got from the backend team. Since there are various factors that might affect the maximum performance of different IO standard of GPIO, we do not guarentee the max performance number, which is also the reason it is not listed in the specification documentation.

 

Thanks.

Eng Wei

View solution in original post

4 Replies
EngWei_O_Intel
Employee
298 Views

Hi there

 

The maximum data rate for general purpose I/O standards is not published as it is depends on design and system specific factors. You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

 

There is only LVDS SERDES IP available in Quartus. Thanks.

 

Eng Wei

Twincreeks
Beginner
288 Views

Hi Eng,

 

Thanks. 

 

In another post https://community.intel.com/t5/Programmable-Devices/Does-Cyclone-10-GX-general-purpose-support-1-434...,

Asked: Does Cyclone 10 GX general-purpose support 1.434 Gbps differential SSTL-12?

Answered: Yes, it will be the same.

It seems that this answer is not well-founded. 

 

Best regards,

Twincreeks

EngWei_O_Intel
Employee
283 Views

Hi Twincreeks

 

This is the understanding we got from the backend team. Since there are various factors that might affect the maximum performance of different IO standard of GPIO, we do not guarentee the max performance number, which is also the reason it is not listed in the specification documentation.

 

Thanks.

Eng Wei

GLees
New Contributor I
253 Views

In other words, Intel is saying they will not give you ANY indication of the maximum achievable performance of an I/O standard.  You have to figure this out for yourself.  This is complete nonsense.  At the very least they should point to one or more reference designs and tell you what the maximum performance was under THOSE conditions.  At least that way you have SOME idea of what MIGHT be achievable.  Yet another reason for migrating to Xilinx..........

Reply