What is the maximum processing speed of NIOS II?

[Altera_Forum]

HI, 

 I know that NIOS II can be clocked to a maximum of 185MHz, and it has 6 pipeline stages, wouldn't the processing speed be 185Mhz as well?? Otherwise, what's the effective processing speed then? Does anyone has any experience on this?   Michael

[Altera_Forum]

speaking from a theoretical point of view the effective processing speed would be 6*185Mhz, where the processor would process 4 instruction for 24 clock cycles without pipelining with pipelining it'll process (or atleast start processing) 24 instructions.. 

but this is only if there are no jump instructions in the program. where as the processor will have to dump all the pipelined instructions before the jump and start over from the new set of instructions. so the effective processing speed is dependent on your program aswell as the nios processor version. because some versions support instruction prediction for effective pipelining.

[Altera_Forum]

There cannot be more instructions processed than are started: only 1 instruction can be completed per cycle so 6 * 185 cannot be. The max is 185 and it is not only branches that degrade, it is any dependency where an instruction depends on the results of a previous instruction. of course not as severe as branches. Another thing to watch for when looking at benchmarks is compiler optimizations of the benchmark code that make it look like more than 1 instruction executes per cycle. Cache misses that stall the pipeline have to be considered ... usually by factoring in the cache hit ratio.

[Altera_Forum]

true only one instruction can be completed in 6 clock cycles but 19 instructions can be completed in 24 clock cycles(if there are no branches or denpendencies as simknutt has stated) so the amount of instructions completed for n number of cycles would be n-5. so when we are considering a large value of time the -5 becomes insignificant and the effective processing speed reaches 185*6. so wouldnt the maximum speed be 185*6?(mathematically speaking its a limit reaching 185*6 as time increases) 

correct me if im wrong :)

[Altera_Forum]

--- Quote Start ---  true only one instruction can be completed in 6 clock cycles but 19 instructions can be completed in 24 clock cycles(if there are no branches or denpendencies as simknutt has stated) so the amount of instructions completed for n number of cycles would be n-5. so when we are considering a large value of time the -5 becomes insignificant and the effective processing speed reaches 185*6. so wouldnt the maximum speed be 185*6?(mathematically speaking its a limit reaching 185*6 as time increases) correct me if im wrong :)  --- Quote End ---    In the above example the speed in instructions per cycle is 19/24. (19/24 * 185Mhz) and if there were enough inline with no interference the 19/24 would approach 1, not 6, therefore the limit is 185Mhz. Unfortunately conditional branches may be 20 to 25% of the mix so the cases where the 6 cycles in the pipeline are negligible are rare.

[Altera_Forum]

hehe my bad.. all the time i was comparing the pipeline to a non-pipelined processor in my head. so the pipelined version would have 6*(the effective processor speed of a non-pipelined system) but the maximum you can achieve is the clock speed. sorry for my mistake :)

[Altera_Forum]

I could not figure where the 5* came in .. wondered if you were thinking multicore, but now I see. An easy mistake to make. As an aside, I think there is a comparison(maybe not really apples and oranges) that shows the non pipelined version vs pipelined and it is nowhere near the theoretical max. If programmers would learn to not use so many branches, things would run a lot faster. Have fun.