Programmable Devices

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Programmable Devices

Discussions

setup time and hold time

MAX3512AFI256-10 programming issue

quartus_hps with qspi in quad mode

Floating point addition in vhdl

DE2i-115 LCD 16x2

Why change phase of PLL doesn't improve clock skew?

The performance of FPGA is not the same when I download the sof file into the FPGA

Cite Altera in my paper

Clock problem

What dose local_size make for ddr2 hpcii?

Max 10 Bank 8 set 1.2V ?

Constraining PLL and Clock control block

connecting 4 GPIO pins to DAC using SPI interface

Arria V A5 FPGA fPLL and it's c-counters power supply

MAX 10 ADC .SOF works, ADC in .POF does not

Featured Content

AGILEX5 - HPS-first - timeout waiting for RECONFIG_COMPLETED

10M04SCU324I7G - I/O timing

SDI pinning on Agilex 5

I350 igb driver failed with error -2

Request for the Product Lifecycle Status

Re: USB Blaster selection criteria

Solution: USB Blaster Driver for Windows 11 ARM