Hi,
I am using a cyclone V SOC fpga. I have a general question about the recommended way to treat a ddr differential input clock. I am working on a project where I am mimicing a mddr chip. So I have to write and read data with an incomming differential clock like a ddr chip would. I am using a
ALTDDIO_BDIR for the data path. My question is what would be the recommended circuit for the incomming clock? Do I connect it to an LVDS reciever and feed the input to a PLL? Then put a single ended PLL output to the outclock of the ALTDDIO_BDIR? There are lots of examples on memory interfaces driving the diff clock out but I didn't find any on bringing it in with the DDIO buffers.
Thanks!
