What should I do if I see this message in the Qsys parameter message?

[Altera_Forum]

What should I do if I see this message in the Qsys parameter message? Is it a support issue? 

  https://alteraforum.com/forum/attachment.php?attachmentid=15677&stc=1  <Error Message >  Info: Platform Designer Tip: Please Sync All System Infos before attempting to resolve the following error messages Error: pcie_qsys_pcie_a10_hip_0.pcie_a10_hip_0: The current value "Avalon-MM with DMA" for parameter "Application interface type" is invalid under setting Interface Width="64-Bit". Error: pcie_qsys_pcie_a10_hip_0.pcie_a10_hip_0: The current value "Avalon-MM with DMA" for parameter "Application interface type" (interface_type_hwtcl) is invalid. Possible valid values are: "Avalon-ST" "Avalon-MM". . Rule(s): interface_type_hwtcl. Info: pcie_qsys_pcie_a10_hip_0.pcie_a10_hip_0: device_family is Cyclone 10 GX Info: pcie_qsys_pcie_a10_hip_0.pcie_a10_hip_0: base_device is NIGHTFURY1 Info: pcie_qsys_pcie_a10_hip_0.pcie_a10_hip_0: part_trait_device is 10CX150YF672E6G Info: pcie_qsys_pcie_a10_hip_0.pcie_a10_hip_0: Inside validate_wrala_hwtcl Info: pcie_qsys_pcie_a10_hip_0.pcie_a10_hip_0: wrala_hwtcl is 6 Info: pcie_qsys_pcie_a10_hip_0.pcie_a10_hip_0: app_interface_width_hwtcl is 64-bit Info: pcie_qsys_pcie_a10_hip_0.pcie_a10_hip_0: link_width_hwtcl is x1 Info: pcie_qsys_pcie_a10_hip_0.pcie_a10_hip_0: lane_rate_hwtcl is Gen1 (2.5 Gbps) Info: pcie_qsys_pcie_a10_hip_0.pcie_a10_hip_0: Gen1 (2.5 Gbps) x1 64-bit

[Altera_Forum]

Hi. Looks like it doesn't like the 64 bit wide DMA setting. Is 64 bit allowed and compatible with the other blocks? Can you try setting DMA to 32 bit?

[Altera_Forum]

Hi. BillyZDSP 

 I am trying this for the first time. I used the samples included in qsys PCIe HardIP.  How can I set DMA to 32bit? Is there a component that can set DMA?  I have a PCIe RC configured as a master and want to link gen1x1 of the cyclone 10 [EP] via the backplane. The RC uses 32bit address structure. How can I link?