What the relative timing relations between 2 clocks out of the PLLs？

[Altera_Forum]

Hi all: 

  I have a question about PLL’s output clocks. In my project, the input clock is 100MHz. I generate a 387.5MHz clock using PLL with multiplying/dividing factor of (32/8), and another clock is 20MHz. The 20MHz clock feeds into another PLL, and generate a 33.68MHz clock with multiplying/dividing factor of (32/19). My question is what are the timing relations between 387.5MHz and 33.8MHz clocks? Someone told me that there are 256 different relative timing relations between them, is it right? And what’s the reason? Thanks in advance!

[Altera_Forum]

The timing relation can be characterized by a defined initial phase on PLL reset. Due to the rational 8/19 frequency ratio of both outputs this isn't much better than unrelated clocks, I think. 

 P.S.: I reviewed your post and found that you are apparently talking about independent 20 and 100 MHz input clocks. In this case, theirs no timing relation between PLL outputs of course.

[Altera_Forum]

Minor point but I think you meant to say (31/8) to get 387.5 MHz from 100 MHz input clock. Also, (32/19) for an input clock of 20 MHz yields a ~33.68 MHz output clock. If you have a clock crossing between the 387.5 MHz clock and the 33.68 MHz clock, you cannot time this accurately in TimeQuest as you will most likely get a 1 ps Setup Relationship since they are not integer multiples of each other. You will have to synchronize this clock crossing and then create a false_path constraint between the clocks.

[Altera_Forum]

Hi FvM&jimbo: 

 Thanks for you reply! I want to emulate random “HITs” for my system, instead of analyzing these clocks. PLL will generate a low speed clock as the HITs(pulse’s edges), and a high speed clock to check the relations between HITs and the closest edge of the high speed clock. So I want to get as much as possible relations between the low speed clock’s edge and high speed clock’s edge. For example, there is only one possibility phase relation between 25MHz clock 250MHz. However, there may be many possibilities between 250MHz and 31.234565789MHz. My question is that I must find a way to know how many possibilities in this example. I just mean discussing it theoreticly, and skip the clock skew, jitter and so on.