I have a 100 MHz clock fed to FPGA on board from an external board.Two similar boards are present in the system.Same 100Mhz clock is fed to both boards on the system.This 100MHz clock is input to a pll in FPGA and generated a 50MHz clock.
I want to make sure that the maximum clock skew between the boards from FPGA input pin to pll output is within a range for all PVT variations.What constraints can be given for the clock path from FPGA input pin to pll output?
Does this mean that you have one clock source to be fed into two different designs? If you want to set data path skew in one design, you may use set_max_skew
Same clock is fed to two different boards in a system that performs similar function.The FPGA program that runs on both boards are same.
I want to make sure the clock skew from the source(FPGA input pin)to PLL output that feeds my logic is within a range of ps. In hardware they have taken care that source clock reaches both FPGA at the same time. This is to make sure that the logic works on both FPGAs in different boards works concurrently without delay.
If the pin location for the source (FPGA input pin) and the PLL are the same in both boards, the clock delay will be the same since the boards are the same.
But the pll in both boards may not lock at the same.There might be skew in the clock output from PLL in these boards if the PLLs gets locked at different instant.
Also these boards might be in different PVT conditions that might contribute to the skew.
set_clock_uncertainty specifies clock uncertainty or skew for clocks or clock-to-clock transfers but it is not for performing maximum allowable skew analysis between sets of clocks.