When Do MSEL pins become valid

[Altera_Forum]

A question, which In could not answer from the lit so far: 

 Does it make any difference, if the MSEL pins are driven by a host to be free of the type of loading procedure? Will there be a power up problem, when the FPGA starts and the MSELs are not driven yet?  I am using a Cycline as a second device, driving MSEL0/1 + nCE by the host. From my understanding, the MSELs only need to be valid, before the nCE-pin becomes active (low) ?  Is that correct - or are the MSELs scanned at start up?  How does this relate to the nConfig?  From my understanding, it should be ok, to just drive the three pins MSEL0/1 + nCe and then drive nConfig afterwards beginning a "warm start" ?:confused:  And one more possible problem:  In case, the host not configured and does not drive the nCE - will it be possible to load the FPGA via JTAG manually?

[Altera_Forum]

You don't refer to a particular device. In the Cyclone 3 handbook, I don't see a hint, that MSEL can be controlled dynamically. In contrast, there are many warnings that suggest to hardwire the pins. It's not explicitely said, when MSEL is read respectively latched, but I would rather expect at POR (after VCCA and VCCINT reach the specified level).  

 It's also said, that nCE must be driven low to use JTAG configuration.

[Altera_Forum]

Thanks so far, I intend to use a Cyclone II - but I do not think it makes a big difference. 

 So now that means, it is not possible to keep the option to switch to another configuration scheme?  For some reasons I would like to use both processor based configuration and platform flash, since I want to adapt to two PCBs:  The old board has no platform flash, while the new one has MCU anymore. But both boards should be equipped with the same header board carrying the cyclone environment.

[Altera_Forum]

Hi, 

What you can do is have a set of 1by3 headers to select the required MSEL settings, the MSEL pin to pin 2 and the supply rails to 1 and 3 as required.

[Altera_Forum]

Ha, of course - but my module was intended to configure itself according to the recognized board version.  

 ok then, it seems I better drop that thought.:o

[Altera_Forum]

Actually, I don't know, how the MSEL hardware is exactly operating nor if it's identical for Cyclone II and Cyclone 3. I guess, you have to do some tests to know for sure. 

 The Cyclone II handbook may be understand like MSEL is read in with a reconfiguration request (nConfig assertion most likely). It also repeats the usual warnings.   --- Quote Start ---  During power-on reset (POR) and reconfiguration, the MSEL pins have to be at LVTTL VIL or VIH levels to be considered a logic low or logic high, respectively. ... The MSEL[] pins should not be driven by a microprocessor or another device.  --- Quote End ---   It should be expected, that the warnings aren't given without a purpose. Together with the remark, that MSEL must not float, although it should be ignored for JTAG configuration mode, it sounds like a problem that can arise when MSEL is undefined at certain times, e.g. during POR. If I remember right, it has been said somewhere, that the configuration logic can be locked in this case.  I assume, that you can drive MSEL from user logic, if you take care that it doesn't expose an undefined level during power on, which can be achieved by specific hardware, e.g. strong pull-up/pull-down resistors. Then you can evaluate, if an MSEL configuration change takes effect in a reconfiguration attempt. Possibly, it does.  Good luck, Frank

[Altera_Forum]

Check page 6 of this document: 

http://www.altera.com/literature/hb/cfg/cfg_cf51001.pdf   May provide a clue to when MSEL pins are sampled. From the state machine shown, it's unknown if MSEL is sampled when entering or leaving the RESET state. You could open a service request and ask for clarification.

[Altera_Forum]

Yes, it should be assumed, that the state-diagram in the config handbook is based on valid information. The sentence quoted above regarding MSEL state during POR is also written in the config handbook.  

 Obviously, devices as Cyclone 3, that have a variable POR time depending on MSEL must sample it at reset.