Why 10AS016C4U19E3SG could use the x16 DDR4 component upper byte lane[DQ8~DQ15] for ECC?

[Kevin52]

Hi team,

 there are  three  x16  DDR4  components  【MT40A512M16LY-075:E】 in my  board,    The upper 8 bits of the lastcomponents are used for ECC.  but I  learn about  a rule from Micron  application note：When using a x16 component for ECC, the lower byte lane (DQ[7:0]) must be used for the ECC bits.DDR4 memory is capable of per-DRAM addressability (PDA), and this function is used during the DDR4 device initialization sequence for VREFDQ calibration. PDA is enabled by DQ0, so the lower byte lane must be used and connected to the controller.

Does  Arria10 SOC FPGA has this limitation?     thank you ！

[yoichiK_intel]

Hi

The restrictions on I/O bank usage result from the Arria® 10 HPS having hard-wired connections to the EMIF circuits in the I/O banks closest to the HPS. For any given EMIF configuration, the pin-out of the EMIF-to-HPS interface is fixed. Please refer to the following link for the detail.

https://www.intel.com/content/www/us/en/docs/programmable/683106/24-1-19-2-3/restrictions-on-i-o-bank-usage-for-emif-19588.html

[Kevin52]

Hi,

When using a DDR4  x16 component for ECC, the Upper  byte lane (DQ[15:8])  could be used for the ECC bits?

[yoichiK_intel]

Hi

Yes, Upper  byte lane (DQ[15:8])  could be used for the ECC bits

[Kevin52]

Hi，

 could you please tell me why Arria10 can  support ？ Micron  said  PDA is only enabled by DQ0 , thank you very much！