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RALLA
Beginner
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Why Arria 10 Transceiver calibration fail whenever PCIe hard IP core is added to the design?

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Jeffrey_C_Intel
Employee
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More information about your specific scenario would be helpful (is it the PCIe A10 GXB that is failing - or another?). For what it's worth, If you have PCIe + any other GXBs that are being used, there is a cascading of cal_done signals that requires that any PCIe hard IPs have to be running and calibrate OK (i.e. connected to a PCIe master) and then the cal_done signals are propagated downstream to any other GXBs that might be used and then their calibrations are attempted. So, if you have a hard PCIe GXB that is in a design - and then another that is being used for, say, CPRI or some other function, the CPRI core GXB will not attempt to start calibration until the PCIe hard IP GXB has successfully calibrated. This is due to requirement for CVP (config via protocol) where PCIe needs to be a the default / first interface configured.

 

Bottom line: In a design that uses PCIe GXBs + anything else, you need a PCIe reference clock that's valid before any of the other GXBs can calibrate.

 

Refer to section 7.3 (page 582) of the following doc:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr...

 

Based on your title and lack of info, this is an educated guess on what might be happening. I've seen this in practice - no other GXBs calibrate if a PCIe core is used in design - but doesn't happen to be connected.

 

Jeff

 

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2 Replies
Jeffrey_C_Intel
Employee
101 Views

More information about your specific scenario would be helpful (is it the PCIe A10 GXB that is failing - or another?). For what it's worth, If you have PCIe + any other GXBs that are being used, there is a cascading of cal_done signals that requires that any PCIe hard IPs have to be running and calibrate OK (i.e. connected to a PCIe master) and then the cal_done signals are propagated downstream to any other GXBs that might be used and then their calibrations are attempted. So, if you have a hard PCIe GXB that is in a design - and then another that is being used for, say, CPRI or some other function, the CPRI core GXB will not attempt to start calibration until the PCIe hard IP GXB has successfully calibrated. This is due to requirement for CVP (config via protocol) where PCIe needs to be a the default / first interface configured.

 

Bottom line: In a design that uses PCIe GXBs + anything else, you need a PCIe reference clock that's valid before any of the other GXBs can calibrate.

 

Refer to section 7.3 (page 582) of the following doc:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr...

 

Based on your title and lack of info, this is an educated guess on what might be happening. I've seen this in practice - no other GXBs calibrate if a PCIe core is used in design - but doesn't happen to be connected.

 

Jeff

 

View solution in original post

Nathan_R_Intel
Employee
100 Views

I agree with Jeff's questions and responses.

 

Basically, more information is needed as following to answer the question:

  • details on your channel and PLL usage. Please advice if only PCIe interface is used or other interface IPs are used on the transceiver channels. Also include details on which location is used for which interface IP.
  • please advice if calibration fail for PCIe or other channels
  • how do you conclude calibration fail? is it based on tx_cal_busy or pll_cal_busy

 

Also, typically PCIe is placed in the bottom channel; and hence the calibration starts from the bottom channel. Making an educated guess, I am suspecting the PCIe link is failing calibration. One of the potential reason is no refclk to PCIe.

 

Please provide the details above to help answer your question.

 

Regards,

Nathan

 

 

 

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