Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Why can't I generate a PCIe example design?

allen18
New Contributor I
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allen18_0-1693810653981.pngallen18_1-1693810661881.png

 

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wchiah
Employee
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Hi,


Can I know which version of quartus you are using ?


Normally this error happen when

When you clean project, the folder of IP in your case XXX.ip is being deleted.

Therefore, you have to re-generate HDL of XXX.ip before you can generate HDL of your qsys system.

Then add_fileset_file "file not found" error should be resolved.


Regards,

Wincent_Intel


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wchiah
Employee
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Hi,


You should click the "Reply" before you can post the "Post Reply"

Can you please provide me the device OPN ? I will try to replicate this on my place and see if I can see the same error as yours or not.



Regards,

Wincent_Intel


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wchiah
Employee
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Hi,


Can I get your agreement to close this loop as replicate ?

we shall move our conversation to https://community.intel.com/t5/forums/forumtopicpage/board-id/programmable-devices/message-id/92371#M92371

For better tracking purpose, do you agree ? Let me know if you have different thoughts.


Regards,

Wincent_Intel


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