Why does Agilex-F PCIe RP IP example design assign the P0 to PCIe lane#0-3 instead of lane#4-7 ?

[seanw_skhms]

One question about the port assignment in the Agilex-F PCIe RP IP example design.

The Agilex-F PCIe RP IP has four of RP x4 bifurcation, and only the P0 core is exported in the example design, which is assigned to PCIe lane#0-3 in the "pin planner". But according to PCIe IP document, UG-20237 table-57, the P0 is mapping to the PCIe lane#4-7 (instead of lane#0-3) in P-Tile 4x4 mode. I am so confused about the mapping between port# and core# by this example design.

Thanks.

Xiao

[BoonT_Intel]

Hello Sir,

The Table 57 is the bifurcation mode which is not available yet for current quartus version with 4x4 configuration.

For non-bifur mode, you can assign the port0 to any lane. You can refer to figure 4/5 for better understanding.

[seanw_skhms]

Hi,

I am getting more confused by your words now. What do you mean by “non-bifurcation mode”? Is it possible to use the ”non-bifurcation mode” and to map the P0 core to the lane#8-11 in the same RP 4x4 example design you sent me? If so, I would like to get a demo code.

What I learned before from Intel FPGA support, see the attached received message, is that the bifurcation modes shown in Table-57 are supported by the Quartus rev-20.2, which matches with the connection drawing shown in Figure-4.

I understood that the Quartus v20.2 does not support the full control over the “bifurcation mux” hardware. But it should be able to support the set of port bifurcation muxes shown by the Table-57.

Since the example design you sent me uses the 4x4 configuration, I still think that the P0 core can only be mapped to lane#4-7 (the lane#0-3 are used by P2 core) by the 4x4 bifurcation mode shown in the table-57.

Best Regards,

Xiao

[BoonT_Intel]

Hi Sir,

The same document already stated there:

Port bifurcation for Gen3 x8, Gen4 x8 and Gen4 x4 will be available in a future release of Intel Quartus Prime.

It is not yet available for current quartus version.

I think you can try to change the location assignment and re-compile and see Quartus let you change it to lane#4-7.

[seanw_skhms]

I am using Quartus V20.2, and the P-Tile AVMM PCIe IP version 3.0.0. The IP generation tool GUI shows the options for using "Gen4X8/Gen4X8 EP" and "Gen4X4/Gen4X4/Gen4X4/Gen4X4 RP" configuration modes, which matches with the table-6 (also table-57) in UG-20237.

I have tried to use lane#4-7 in the "Gen4X4/Gen4X4/Gen4X4/Gen4X4 RP" configuration mode. Both of the synthesis and fit reports are showing expected connection without giving me any errors. But since the simulation is not supported for the 4x4 RP configuration in the current version of tool, it can only be verified in lab later.

regards,

Xiao

[BoonT_Intel]

For PCIe link configuration, it will configure based on the effective lane. For example, an upstream device has X16 lane. However, the down stream device only has x4 lane, regardless you connect the x4 downstream device to which lane order of the upstream device (mean regardless to you connect it to lane 0-3 or 4-7). The upstream device will proceed with a group of lanes that can still be used to create a link. Mean it will link up with x4 configuration. In this case, the link-up is 1-1, same with what we want to achieve in the example design. This is not a bifurcation mode.

For bifurcation mode, it is referring to splitting 1 PCIe Port into 2 or more with smaller lane width. Example an upstream x16 port into 2downstream x8 port. In this case, the link up is 1 to 2 or more which is not yet support in the P-tile PCIe IP.

Hope this clear.

[seanw_skhms]

Hi,

Let me ask the question in other way.  In the example design you sent me, the P-Tile is configured to the  4X4 RP mode, and on the AVMM bus connection side the jtag-avmm bridge is connected to drive the P0 core only. The question is that when user drives the P0 core through jtag to create a PCIe transaction, the PCIe transaction will show up on which X4 lanes group? on the lane#0-3 or lane#4-7 or others?

Thanks,

Xiao

[BoonT_Intel · Accepted solution]

Ok after understanding further by checking the ED Qsys (platform designer).

I can see the JTAG master component is connecting to P0 of the P-tile IP. By right it should connect to channel 4-7 based on table 57. However, we not sure why ED connects it to 0-3, I will check this with the internal team but will need some time.

However, for urgent sake, you can try the approach by using lane 4-7 for the example design. If not working, then we will give a try on other port (by changing the connection in the Qsys) or another lane on assignment editor.

[seanw_skhms]

Thanks for your confirmation.

Best regards,

Xiao

[BoonT_Intel]

You're welcome.