Recently I have met a problem.My fpga is ep4ce115f23c8 and I use the DDR and DDR2 SDRAM High-Performance Controller IP core to control the DDR2 MT47H64M16HR. Usually it works well.But sometimes the IP core can't read out any data.The local_init_done signal is high.And I have send the read address to the IP core.The only useful method is set the global_reset_n sigal down for a while and then set it high.But what's the reason?Can any one tell me the reason?
Hi vlrean,I checked the problem,but when I asserted read request,the local_ready is high.When I send my read commands,there is no write commands.I send the read address sucessfully,all works well,but data don't come out.I want to read out 1024 data,but sometimes only come out hundreds of them,or no data come out.I get my pll_ref_clk from a external crystal which is 50MHz,am I right?Shall the pll_ref_clk come from a pll?
What board are you using? Some dev kit or custom made board?Have you verified DDR2 memory with Altera example design? Have you checked that all your signals are asserted correctly (local_read_req, local_burstbegin, local_size ect...) when local_ready goes down? Yes, it is OK to provide clock to pll_ref_clk from external crystal. You have to set DDR2 IP core to same frequency as crystal.