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ethernet phy export to fpga portion

Honored Contributor I

Hi everybody, 


I'm trying to export the ethernet phy RGMII interface of our de10-nano board to the fpga portion. The phy is connected to the hps and not directly to the fpga. 

I want to control the phy from fpga. 

In qsys I selected full export in the peripheral pins tab hps. According to this example ( ), the RGMII interface is then supposed to be exported to the fpga as GMII.  

My problem is that the MDIO interface clock has direction OUTPUT, which does not make sense, right? 

Also the gtx_clock is OUTPUT instead of input... 


Did I misunderstand the usage of this export functionality? Is this just for 'listening' on the ethernet interface and not for controlling it?  

Some clarification would be very appreciated, 

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Honored Contributor I

Yes I think you misunderstood the export functionality, it is actually meant to be used the other way round, i.e. to control from the HPS a PHY that would be connected to FPGA pins. 

To do what you want I think you need to set both EMACs to "unused", find the pins your PHY are connected to in the Peripherals Mux Table and enable the "LOAN" buttons for each of them. I've never done that myself though.