Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Why is the UFM busy all the time?

Altera_Forum
Honored Contributor II
‎09-11-2007 12:42 AM
1,232 Views

I use MaxII EPM570. After finishing the RDSR, WREN, WRSR and SECTOR-ERASE, i find the status register Bit0 is 1 all the time when i execute RDSR again. If the Bit0 is high, i can do nothing then.  

 

Why the Bit0 is high all the time though i wait for a long time? The Bit0 is low when power up and i execute RDSR at first time. 

 

Thanks very much
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Altera_Forum
Honored Contributor II
‎09-11-2007 05:39 AM
540 Views

I have solved it.  

 

In Quartus II, i use simulation to simulate the whole process. In the Simulation Report, it uses about 50us to finish the RDSR, WREN, WRSR and SECTOR-ERASE steps. Then I execute RDSR again to find out whether the erase cycle is still in progress. It uses about 500us to finish SECTOR-ERASE step and set Bit0 to 0. Since the time step which i set in simulation is small(about 150ns), i didn't find the termination of SECTOR-ERASE and thought that the Bit0 was always high.  

 

Now, it can work correctly now.
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Altera_Forum
Honored Contributor II
‎09-11-2007 11:09 AM
540 Views

Known issue with me-))

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