Why "fifoed avalon uart" was removed from web site ?

[RShal4]

Hello,

When using "uart" simple IP we encounter byte lost.

We than moved to "fifoed avalon uart" ver 13.2 which was in alterawiki page.

It solved our byte loss but only partly. When we use several UARTs at the same time, we still encounter byte loss.

We believe there is a bug in this IP sw/fw.

But soon after we started using it, about 2 weeks ago, it was removed from web site! It was in this site:

http://www.alterawiki.com/wiki/FIFOed_Avalon_Uart

Is there any alternative ? Does Intel offer any functional UART with FIFO ?

Thanks,

ranran

[Kenny_Tan]

I see it is not removed. Can you show me the screenshot how it got removed? This component still exist in the platform designer UART (RS-232 serial port)

[RShal4]

Hello,

I am not speaking about UART (rs-232 serial port) but about fifoed avalon uart.

which was in page:

http://www.alterawiki.com/wiki/FIFOed_Avalon_Uart

and we can't access the zip file any more.

Thanks

[Kenny_Tan]

I click on any *zip file in the link I was able to download it. Can you try to use different browser or even different computer to download?

[RShal4]

That is strange.

Are you using link:

http://www.alterawiki.com/wiki/FIFOed_Avalon_Uart

Did you try clicking :"

• fifoed_avalon_uart_13.2.tar.gz - FIFOed Avalon UART v13.2 from 1 Dec 2014 (LATEST RELEASE)"

I've tried with both microsoft explorer and Google chrome. On clicking the zip it moves to another page with a long list of documents.

Thanks,

ran

[Kenny_Tan]

Yes, it had the zip files. I guess I will just attached it here. Let me know if you have more zip files needed from the above link.

[RShal4]

Thank you very much,

Is it that this IP is Intel's IP for FIFO UART or is there another Intel FIFO uart ?

Thanks,

[Kenny_Tan]

This is for FIFOed UART (RS-232 serial port)

[RShal4]

Is there any better IP or better version for using UART ?

Even with 13.2 we see very strange behaviour !

We configure it for 2048 bytes, yet after sending for example 200 bytes, we only find 64 bytes inside (even more strangely is that using the debuger we stop in fifo avalon we see that diff between rx_end and rx-start is only 1, and then doing continue in dubbger we get only 1 !

Is there any functional *FIFO* UART from Intel's IP ?

Thanks,

Ran

[Kenny_Tan]

Hi Ran, How do you check the result? Is it with modelsim or signal tap? The document that I found is https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/nios2/n2cpu_nii51010.pdf Try to screenshot the result that you are seeing so that I can take a look the failure part.

[SKACH2]

Hi, KTan9

But how about other design examples?

For example i can't download this link: https://fpgawiki.intel.com/wiki/File:Modular_SGDMA_DE.zip and other from this page: https://forums.intel.com/s/createarticlepage?articleid=a3g0P0000005R2BQAU&artTopicId=0TO0P000000MWKBWA4&action=view

Will access to these files be restored?

[Kenny_Tan]

I am not sure why you cannot download it, i try from my side and it had no problem at all. What OS that you were using? Try to use few computer rather than 2 computer to see if you can download it?

[Kenny_Tan]

any update?

[rshal2]

Thanks, yes it works fine now.

There was a bug in latest (13.2) release in which the header file set size of fifo as 64, although we needed - and configured - a larger fifo in qsys.

On increasing this size, "bytes skiped issue" been solved.

Thanks