I have a simple verilog program that uses an always loop:
reg [1:0] cnt_b;
always_ff @ (posedge clk_pwm)
cnt_b <= cnt_b + 1;
if (out_4 == 0) out_4 <= 1;
else out_4 <= 0;
I'm outputting the 2 bit cnt_b, clk_pwm, and out_4 onto I/o pins.
On the output pins I'm seeing out_4 toggle and cnt_b increment when no edge occurs on clk_pwm!
What could cause something like this to happen?
Thanks for any help.
- Intel® MAX® 10 FPGAs
I'll answer my own question:
The 'extra' hits in the always loop were from glitches in the clock, creating extra posedges. I wasn't seeing the edges on the outputs because they were to fast to show up on the logic analyzer. (Faster than the sampling rate.)
The solution was to debounce the generated clock signal to get rid of the glitches.