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Valued Contributor III
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Writing the .sdc to the SoC, anything particular? Can't close timing.

Hello, I had a project with no timing problems at a Cyclone IV (EP4CE75F23I7). Now I am porting this same project to a Cyclone V (5CSEMA6U23I7) but I can't close timing, infact, it got much much worse. (I am using Quartus 14.0) 

 

Here is my SDC 

 

create_clock -period 10.000 -waveform { 0.000 5.000 } -name ext_clock derive_pll_clocks -create_base_clocks derive_clock_uncertainty create_clock -name eth0_rx_clk -period "25MHz" create_clock -name eth0_tx_clk -period "25MHz" # Ethernet MAC_0 set_min_delay 0.0 -from eth0_rx_dv eth0_rx_er}] -to * set_max_delay 4.0 -from eth0_rx_dv eth0_rx_er}] -to * set_min_delay 4.0 -from * -to eth0_tx_en}] set_max_delay 12.0 -from * -to eth0_tx_en}] # MDIO_0 set_min_delay 0.0 -from -to * set_max_delay 4.0 -from -to * set_min_delay 4.0 -from * -to set_max_delay 12.0 -from * -to # **************************************************************# Set False Path# ************************************************************** set_false_path -from -to * set_false_path -from -to * set_false_path -from -to * set_false_path -from * -to set_false_path -from * -to set_false_path -from * -to set_false_path -from * -to set_false_path -from -to * set_false_path -from -to * set_false_path -from -to * set_false_path -from -to * set_false_path -from -to * set_false_path -from -to * set_false_path -from -to * set_false_path -from -to * set_false_path -from -to * set_false_path -from * -to set_false_path -from * -to set_false_path -from * -to set_false_path -from -to * set_false_path -from * -to set_false_path -from -to * set_false_path -from * -to set_false_path -from * -to set_false_path -from * -to set_false_path -from * -to set_false_path -from * -to set_false_path -from -to * set_false_path -from * -to set_false_path -from * -to set_false_path -from * -to set_false_path -from -to * set_false_path -from * -to # **************************************************************# I2C Signal Constraints# ************************************************************** # extremely low frequency set_false_path -from -to * set_false_path -from * -to set_false_path -from -to * set_false_path -from * -to # **************************************************************# Delta Sigma Constraints# **************************************************************# create_clock -name {mclkin} -period 25.000 -waveform { 0.000 5.000 } # set_min_delay 4.0 -from * -to # set_max_delay 12.0 -from * -to # set_min_delay 0.0 -from -to *# set_max_delay 4.0 -from -to * set_false_path -from * -to set_false_path -from -to *  

 

Is there anything I can do? Something I am missing between the HPS and the FPGA? 

 

My ext clock (100 mhz) is going directly to an Altera PLL that tries do deliver 100mhz, but it says that its fmax is 90.64 Mhz, which is very weird. 

 

Also when I go to the summary it says that the eth0_tx_clk fmax is restricted to 35.76 mhz and the eth0_rx_clk to 1337 mhz, which I also found very weird because in my sdc I am saying they are a 25 mhz clock. 

 

Any help is appreciated, It's the same project, the only difference is that I took Nios2 away and got a HPS instead.
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Valued Contributor III
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Hello, tell me please, how many hardware memory channels ddr3 can be organized in the chip 5CSEMA6U23I7? I need HPS to work through the first "Hard Memory Controller and Hard Memory PHY", and the FPGA was working through the second "Hard Memory Controller and Hard Memory PHY". Each memory channel uses two ddr3 chips, with a total data bus of 32 bits. Can both interfaces work independently? Can both interfaces operate at the maximum possible frequency for the 5CSEMA6U23I7 chip at 400MHz, provided the "Enable Hard External Memory Interface" checkbox is set?

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