a basic timer in VHDL

[Altera_Forum]

hi, how can I write a program for a timer which counts up to 6.4 micro seconds? 

thanks in advance

[Altera_Forum]

entity timer is end entity timer; architecture time of timer is signal timer : std_logic; begin timer <= '0', '1' after 6.4 us; end architecture time;

[Altera_Forum]

Use a template from Quartus 

 Create a new vhdl file.  Select edit menu->insert template->  Select VHDL->Full Designs->Counters->Binary Count  Then modify then MAX_COUNT value depending on your input clock speed. i.e. how many input clock periods in 6.4us  Templates are agood way of finding out how to code various constructs  Hope this helps

[Altera_Forum]

Tricky gave a solution which is NOT synthesizable. Good for simulation only. 

 I am agree with Vernmid