a question about DSP block mapping

[CHung]

Hi,

We read the following document of S10 dsp block design.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-dsp.pdf

An we have some questions:

1. In figure 1, is there any pipeline register between the Multipliers and Adder?

2. If our design is "multiplier->register->adder->register", could it be mapped to a dsp block?

    Would quartus map it to dsp block, and map the register inside our design to 1st pipeline register and 2nd pipeline register in figure 1?

Thanks.

[CheePin_C_Intel · Accepted solution]

Hi,

Sorry for the delay. As I understand it, you have some inquiries related to the S10 DSP block. Please see my responses as following:

1. In figure 1, is there any pipeline register between the Multipliers and Adder?

[CP] For your information, the figure is showing the functional representation of the DSP block. Based on it, there is no pipeline register between multiplier and adder. Sorry for the inconvenience.

2. If our design is "multiplier->register->adder->register", could it be mapped to a dsp block? Would quartus map it to dsp block, and map the register inside our design to 1st pipeline register and 2nd pipeline register in figure 1?

[CP] Since the pipeline registers are before the multiplier, it is rather hard for me to tell if Quartus will map your registers to the pipeline registers. I would recommend you to create simple test design and run through Quartus compilation to verify if your design can be mapped and synthesized implemented per your expectation or not.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[Jeffrey_C_Intel]

Is there a very specific use-case for having the register between the multiplier and the adder (other than performance)?  The DSP blocks are optimized for the mult-add operation, so it's likely you shouldn't need that register in between to achieve close to fmax for S10 mult-add.  I created a quick test design in DSP Builder and it was able to achieve >800MHz operation (just DSP block) with a 16b x 16b mult followed by 16b adder.  The module had a latency (in-to-out) of 5 clock cycles to perform the operation.

Ways to instantiate the DSP block explicitly when designing would be the following:

- Select modules from IP menu (customize and instantiate with HDL or Platform Designer)

- Use a high-level tool like DSP Builder

- Use a template with HDL to select a topology and instantiate (right-click in HDL editor)

Jeff 

[CheePin_C_Intel]

Hi Jeff,

thanks lot for your explanation.

[CheePin_C_Intel]

Hi,

I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.