Re: a way to keep the program when FPGA is disconnected from the USB blaster

Altera_Forum · ‎01-23-2017

Hello,

I was wondering if there is a way to keep the program when FPGA is disconnected from the USB blaster?

I am working with DE2 and DE0 boards..

I tried with Active Serial Mode Programming, but it is only useful to keep the program when FPGA is disconnected from the power supply

Thank you

Altera_Forum · ‎01-23-2017

Both the DE0 and DE2 (and in fact all the DEx boards) have a serial program EEPROM attached to the FPGA. You can download a configuration into this EEPROM, and it can then be automatically loaded into the FPGA when it powers on. No need to have a USB Blaster attached, just need to power the board with a plain AC adapter.

Look for: altserial_flash_loader on the altera website, it is a function you can instantiate into your top level module that then puts the serial EEPROM into the JTAG chain so you can save a program into it via the Altera Quartus Programming software.

The first time you generate an image for your FPGA (assuming it is blank or has not had SFL enabled previously) the EEPROM won't appear in the JTAG chain, just the FPGA does. So then manually load the generated SOF file into the FPGA config RAM, and then reconnect to the board. You should then see an additional JTAG device (the EEPROM) appear in the chain, and you can assign the JIC file to it.

For example here is the module instance I use it my top level verilog module:


    // Altera Serial Flash Loader module
    // Allows external JTAG access to the serial config eeprom for programming
    sfl    sfl
    ( .asdo_in        (1'b0),        // not used
      .dclk_in        (1'b0),        // not used
      .ncso_in        (1'b0),        // not used
      .noe_in        (1'b0),        // always enabled
      .asmi_access_granted    (1'b1),        // external JTAG access always
      .asmi_access_request    (),        // not used
      .data0_out        ()        // not used
      );

And here is the (megawizard) generated module I include with the design:

// megafunction wizard: %Serial Flash Loader%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altserial_flash_loader 
// ============================================================
// File Name: sfl.v
// Megafunction Name(s):
//             altserial_flash_loader
//
// Simulation Library Files(s):
//             altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfl (
    asdo_in,
    asmi_access_granted,
    dclk_in,
    ncso_in,
    noe_in,
    asmi_access_request,
    data0_out);
    input      asdo_in;
    input      asmi_access_granted;
    input      dclk_in;
    input      ncso_in;
    input      noe_in;
    output      asmi_access_request;
    output      data0_out;
    wire  sub_wire0;
    wire  sub_wire1;
    wire  asmi_access_request = sub_wire0;
    wire  data0_out = sub_wire1;
    altserial_flash_loader    altserial_flash_loader_component (
                .noe (noe_in),
                .scein (ncso_in),
                .asmi_access_granted (asmi_access_granted),
                .dclkin (dclk_in),
                .sdoin (asdo_in),
                .asmi_access_request (sub_wire0),
                .data0out (sub_wire1)
                // synopsys translate_off
                ,
                .data_in (),
                .data_oe (),
                .data_out ()
                // synopsys translate_on
                );
    defparam
        altserial_flash_loader_component.enable_quad_spi_support = 0,
        altserial_flash_loader_component.enable_shared_access = "ON",
        altserial_flash_loader_component.enhanced_mode = 1,
        altserial_flash_loader_component.intended_device_family = "Cyclone IV E";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_QUAD_SPI_SUPPORT NUMERIC "0"
// Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "ON"
// Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: USED_PORT: asdo_in 0 0 0 0 INPUT NODEFVAL "asdo_in"
// Retrieval info: USED_PORT: asmi_access_granted 0 0 0 0 INPUT NODEFVAL "asmi_access_granted"
// Retrieval info: USED_PORT: asmi_access_request 0 0 0 0 OUTPUT NODEFVAL "asmi_access_request"
// Retrieval info: USED_PORT: data0_out 0 0 0 0 OUTPUT NODEFVAL "data0_out"
// Retrieval info: USED_PORT: dclk_in 0 0 0 0 INPUT NODEFVAL "dclk_in"
// Retrieval info: USED_PORT: ncso_in 0 0 0 0 INPUT NODEFVAL "ncso_in"
// Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
// Retrieval info: CONNECT: @asmi_access_granted 0 0 0 0 asmi_access_granted 0 0 0 0
// Retrieval info: CONNECT: @dclkin 0 0 0 0 dclk_in 0 0 0 0
// Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
// Retrieval info: CONNECT: @scein 0 0 0 0 ncso_in 0 0 0 0
// Retrieval info: CONNECT: @sdoin 0 0 0 0 asdo_in 0 0 0 0
// Retrieval info: CONNECT: asmi_access_request 0 0 0 0 @asmi_access_request 0 0 0 0
// Retrieval info: CONNECT: data0_out 0 0 0 0 @data0out 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

And here is the COF file I feed into the quartus create programming file tool to transform the SOF to the required JIC file:

<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
    <eprom_name>EPCS64</eprom_name>
    <flash_loader_device>EP4CE22</flash_loader_device>
    <output_filename>DE0_PDP8.jic</output_filename>
    <n_pages>1</n_pages>
    <width>1</width>
    <mode>7</mode>
    <sof_data>
        <user_name>Page_0</user_name>
        <page_flags>1</page_flags>
        <bit0>
            <sof_filename>DE0_PDP8.sof</sof_filename>
        </bit0>
    </sof_data>
    <version>4</version>
    <options>
        <map_file>1</map_file>
    </options>
</cof>

And here is the CDF (chain descriptor file) I use within Quartus Programmer to actually download a new program to the EEPROM:

/* Quartus II Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition */
JedecChain;
    FileRevision(JESD32A);
    DefaultMfr(6E);
    P ActionCode(Cfg)
        Device PartName(EP4CE22F17) Path("") File("DE0_PDP8.sof") MfrSpec(OpMask(1) SEC_Device(EPCS64) Child_OpMask(1 3) SFLPath("DE0_PDP8.jic"));
ChainEnd;
AlteraBegin;
    ChainType(JTAG);
AlteraEnd;

Altera_Forum · ‎01-23-2017

--- Quote Start ---

Both the DE0 and DE2 (and in fact all the DEx boards) have a serial program EEPROM attached to the FPGA. You can download a configuration into this EEPROM, and it can then be automatically loaded into the FPGA when it powers on. No need to have a USB Blaster attached, just need to power the board with a plain AC adapter.

Look for: altserial_flash_loader on the altera website, it is a function you can instantiate into your top level module that then puts the serial EEPROM into the JTAG chain so you can save a program into it via the Altera Quartus Programming software.

The first time you generate an image for your FPGA (assuming it is blank or has not had SFL enabled previously) the EEPROM won't appear in the JTAG chain, just the FPGA does. So then manually load the generated SOF file into the FPGA config RAM, and then reconnect to the board. You should then see an additional JTAG device (the EEPROM) appear in the chain, and you can assign the JIC file to it.

For example here is the module instance I use it my top level verilog module:


    // Altera Serial Flash Loader module
    // Allows external JTAG access to the serial config eeprom for programming
    sfl    sfl
    ( .asdo_in        (1'b0),        // not used
      .dclk_in        (1'b0),        // not used
      .ncso_in        (1'b0),        // not used
      .noe_in        (1'b0),        // always enabled
      .asmi_access_granted    (1'b1),        // external JTAG access always
      .asmi_access_request    (),        // not used
      .data0_out        ()        // not used
      );

And here is the (megawizard) generated module I include with the design:

// megafunction wizard: %Serial Flash Loader%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altserial_flash_loader 
// ============================================================
// File Name: sfl.v
// Megafunction Name(s):
//             altserial_flash_loader
//
// Simulation Library Files(s):
//             altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfl (
    asdo_in,
    asmi_access_granted,
    dclk_in,
    ncso_in,
    noe_in,
    asmi_access_request,
    data0_out);
    input      asdo_in;
    input      asmi_access_granted;
    input      dclk_in;
    input      ncso_in;
    input      noe_in;
    output      asmi_access_request;
    output      data0_out;
    wire  sub_wire0;
    wire  sub_wire1;
    wire  asmi_access_request = sub_wire0;
    wire  data0_out = sub_wire1;
    altserial_flash_loader    altserial_flash_loader_component (
                .noe (noe_in),
                .scein (ncso_in),
                .asmi_access_granted (asmi_access_granted),
                .dclkin (dclk_in),
                .sdoin (asdo_in),
                .asmi_access_request (sub_wire0),
                .data0out (sub_wire1)
                // synopsys translate_off
                ,
                .data_in (),
                .data_oe (),
                .data_out ()
                // synopsys translate_on
                );
    defparam
        altserial_flash_loader_component.enable_quad_spi_support = 0,
        altserial_flash_loader_component.enable_shared_access = "ON",
        altserial_flash_loader_component.enhanced_mode = 1,
        altserial_flash_loader_component.intended_device_family = "Cyclone IV E";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_QUAD_SPI_SUPPORT NUMERIC "0"
// Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "ON"
// Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: USED_PORT: asdo_in 0 0 0 0 INPUT NODEFVAL "asdo_in"
// Retrieval info: USED_PORT: asmi_access_granted 0 0 0 0 INPUT NODEFVAL "asmi_access_granted"
// Retrieval info: USED_PORT: asmi_access_request 0 0 0 0 OUTPUT NODEFVAL "asmi_access_request"
// Retrieval info: USED_PORT: data0_out 0 0 0 0 OUTPUT NODEFVAL "data0_out"
// Retrieval info: USED_PORT: dclk_in 0 0 0 0 INPUT NODEFVAL "dclk_in"
// Retrieval info: USED_PORT: ncso_in 0 0 0 0 INPUT NODEFVAL "ncso_in"
// Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
// Retrieval info: CONNECT: @asmi_access_granted 0 0 0 0 asmi_access_granted 0 0 0 0
// Retrieval info: CONNECT: @dclkin 0 0 0 0 dclk_in 0 0 0 0
// Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
// Retrieval info: CONNECT: @scein 0 0 0 0 ncso_in 0 0 0 0
// Retrieval info: CONNECT: @sdoin 0 0 0 0 asdo_in 0 0 0 0
// Retrieval info: CONNECT: asmi_access_request 0 0 0 0 @asmi_access_request 0 0 0 0
// Retrieval info: CONNECT: data0_out 0 0 0 0 @data0out 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfl_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

And here is the COF file I feed into the quartus create programming file tool to transform the SOF to the required JIC file:

<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
    <eprom_name>EPCS64</eprom_name>
    <flash_loader_device>EP4CE22</flash_loader_device>
    <output_filename>DE0_PDP8.jic</output_filename>
    <n_pages>1</n_pages>
    <width>1</width>
    <mode>7</mode>
    <sof_data>
        <user_name>Page_0</user_name>
        <page_flags>1</page_flags>
        <bit0>
            <sof_filename>DE0_PDP8.sof</sof_filename>
        </bit0>
    </sof_data>
    <version>4</version>
    <options>
        <map_file>1</map_file>
    </options>
</cof>

And here is the CDF (chain descriptor file) I use within Quartus Programmer to actually download a new program to the EEPROM:

/* Quartus II Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition */
JedecChain;
    FileRevision(JESD32A);
    DefaultMfr(6E);
    P ActionCode(Cfg)
        Device PartName(EP4CE22F17) Path("") File("DE0_PDP8.sof") MfrSpec(OpMask(1) SEC_Device(EPCS64) Child_OpMask(1 3) SFLPath("DE0_PDP8.jic"));
ChainEnd;
AlteraBegin;
    ChainType(JTAG);
AlteraEnd;

--- Quote End ---

Is this EEPROM is EPCS?

Altera_Forum · ‎01-23-2017

Technically Spansion S25FL064P1F (EPCS64 clone) FLASH / EEPROM memory.

--- quote start ---

nonetheless, today's trend seems to be to use the term "eeprom" for devices with per-byte erase capabilities and "flash" for devices which only support large-block erasure. flash is a type of eeprom (electrically erasable programmable read-only memory). "flash" is more of a marketing term than a specific technology.

--- quote end ---

EEPROM is a more generic term, didn't mean to confuse you.