about "create a clk in TA"

[Altera_Forum]

I used some wire or register to be a clk . but i dont assign a clk attribute to it in TA, so i get warning "Warning: Node: global_reset:u7|byte_read_clk was determined to be a clock but was found without an associated clock assignment." 

Because the period of byte_read_clk is not fixed ,it varies a lot. It's style is fisrt with a ringedge clk ,then 6 mute clk ,after that is 23 clk ,after that is 18 mute clk. And next ,a new burst will begin.  so i wanna know should i pay attention to the warning? or should i create a clk attribute for it ? is it meaningful for the Quartus ? thanks !   yu.p

[Altera_Forum]

The tools need timing information. If you don't provide a clock constrain, the tools will just assume a 1 GHz clock. 

 You should create a clock constrain, as close to your real clock as possible. For example, ignore the fact that it's gated (muted) and just specify it's base frequency.  Gating clocks within FPGAs has issues; if possible, it's best to replace gated clocks with clock enables.

[Altera_Forum]

thanks very much ! 

 yes,gated clock may have problem within FPGAs?   you mentioned that there is an option to used clock enables ,do you mean that use a PLL enable to control the generation of clock .

[Altera_Forum]

No, clock enables are a signal for the flip-flop. 

 In Verilog, something like this always @(posedge clk, reset) begin if (reset)  begin // reset goes here end else if (enable)  begin // logic goes here end end  This template will map to logic where the flip-flops have a clock enable input.  In FPGAs, all forms of clocks generated by logic tend to suffer skew and usually they make it harder to achiieve the timmings.

[Altera_Forum]

thanks a lot . i get it !