accessing HPS core SPI master with internal FPGA logic

[Altera_Forum]

Hi, 

 I am trying to access the HPS SPI master outputs/inputs and have it feed to logic inside my CYCLONE V fpga. Is there a way to do this without having to go outside of the FPGA and then hardwire back to input pins of the FPGA.  Thanks  Kumar

[Altera_Forum]

Yes, there is. 

 You need to read "an 706: mapping hps ip peripheral signals to the fpga interface (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an706.pdf)".  Cheers, Alex

[Altera_Forum]

It might be easier, and use less fpga resources to have the fpga interrupt the HPS and have it do the SPI stuff.

[Altera_Forum]

wondering, I remember i saw there is a spi core ip with the fpga, why need to utilize the hps spi core instead? is it more powerful or better stability?

[Altera_Forum]

The one in HPS will operate much faster. Adding an FPGA SPI core uses up resources on the FPGA. What advantage is there to using a core on the FPGA and routing to the HPS pins? It just seems like extra work to me given you already have software in HPS and can add SPI to it. You can use any FPGA pins for SPI so long as you put in ESD protection if it's going to be external.